SPI_HOST Simulation Results

Monday October 06 2025 17:11:21 UTC

GitHub Revision: 0f6fcf0

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_host_smoke	49.000s	10.421ms	1	1	100.00
V1	csr_hw_reset	spi_host_csr_hw_reset	2.000s	20.073us	1	1	100.00
V1	csr_rw	spi_host_csr_rw	1.000s	15.722us	1	1	100.00
V1	csr_bit_bash	spi_host_csr_bit_bash	2.000s	124.252us	1	1	100.00
V1	csr_aliasing	spi_host_csr_aliasing	2.000s	114.980us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	spi_host_csr_mem_rw_with_rand_reset	2.000s	123.507us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_host_csr_rw	1.000s	15.722us	1	1	100.00
		spi_host_csr_aliasing	2.000s	114.980us	1	1	100.00
V1	mem_walk	spi_host_mem_walk	1.000s	88.305us	1	1	100.00
V1	mem_partial_access	spi_host_mem_partial_access	1.000s	29.418us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	performance	spi_host_performance	1.000s	45.072us	1	1	100.00
V2	error_event_intr	spi_host_overflow_underflow	2.000s	24.327us	1	1	100.00
		spi_host_error_cmd	2.000s	18.629us	1	1	100.00
		spi_host_event	13.000s	2.017ms	1	1	100.00
V2	clock_rate	spi_host_speed	5.000s	418.630us	1	1	100.00
V2	speed	spi_host_speed	5.000s	418.630us	1	1	100.00
V2	chip_select_timing	spi_host_speed	5.000s	418.630us	1	1	100.00
V2	sw_reset	spi_host_sw_reset	8.000s	522.867us	1	1	100.00
V2	passthrough_mode	spi_host_passthrough_mode	1.000s	42.950us	1	1	100.00
V2	cpol_cpha	spi_host_speed	5.000s	418.630us	1	1	100.00
V2	full_cycle	spi_host_speed	5.000s	418.630us	1	1	100.00
V2	duplex	spi_host_smoke	49.000s	10.421ms	1	1	100.00
V2	tx_rx_only	spi_host_smoke	49.000s	10.421ms	1	1	100.00
V2	stress_all	spi_host_stress_all	29.000s	2.966ms	1	1	100.00
V2	spien	spi_host_spien	2.000s	279.664us	1	1	100.00
V2	stall	spi_host_status_stall	32.000s	2.614ms	1	1	100.00
V2	Idlecsbactive	spi_host_idlecsbactive	3.000s	141.527us	1	1	100.00
V2	data_fifo_status	spi_host_overflow_underflow	2.000s	24.327us	1	1	100.00
V2	alert_test	spi_host_alert_test	2.000s	42.253us	1	1	100.00
V2	intr_test	spi_host_intr_test	1.000s	49.306us	1	1	100.00
V2	tl_d_oob_addr_access	spi_host_tl_errors	2.000s	151.565us	1	1	100.00
V2	tl_d_illegal_access	spi_host_tl_errors	2.000s	151.565us	1	1	100.00
V2	tl_d_outstanding_access	spi_host_csr_hw_reset	2.000s	20.073us	1	1	100.00
		spi_host_csr_rw	1.000s	15.722us	1	1	100.00
		spi_host_csr_aliasing	2.000s	114.980us	1	1	100.00
		spi_host_same_csr_outstanding	2.000s	69.542us	1	1	100.00
V2	tl_d_partial_access	spi_host_csr_hw_reset	2.000s	20.073us	1	1	100.00
		spi_host_csr_rw	1.000s	15.722us	1	1	100.00
		spi_host_csr_aliasing	2.000s	114.980us	1	1	100.00
		spi_host_same_csr_outstanding	2.000s	69.542us	1	1	100.00
V2		TOTAL			15	15	100.00
V2S	tl_intg_err	spi_host_tl_intg_err	1.000s	49.866us	1	1	100.00
		spi_host_sec_cm	1.000s	508.081us	1	1	100.00
V2S	sec_cm_bus_integrity	spi_host_tl_intg_err	1.000s	49.866us	1	1	100.00
V2S		TOTAL			2	2	100.00
	Unmapped tests	spi_host_upper_range_clkdiv	3.917m	7.441ms	1	1	100.00
		TOTAL			26	26	100.00