SRAM_CTRL/MAIN Simulation Results

Monday October 06 2025 17:11:21 UTC

GitHub Revision: 0f6fcf0

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	4.400s	1.385ms	1	1	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	0.750s	29.497us	1	1	100.00
V1	csr_rw	sram_ctrl_csr_rw	0.750s	40.224us	1	1	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	1.820s	751.276us	1	1	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	0.710s	41.822us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	2.350s	347.213us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	0.750s	40.224us	1	1	100.00
		sram_ctrl_csr_aliasing	0.710s	41.822us	1	1	100.00
V1	mem_walk	sram_ctrl_mem_walk	2.091m	25.637ms	1	1	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	1.859m	18.326ms	1	1	100.00
V1		TOTAL			8	8	100.00
V2	multiple_keys	sram_ctrl_multiple_keys	13.198m	35.973ms	1	1	100.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	2.620m	3.334ms	1	1	100.00
V2	bijection	sram_ctrl_bijection	22.083m	98.794ms	1	1	100.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	3.135m	27.012ms	1	1	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	6.850s	1.467ms	1	1	100.00
V2	executable	sram_ctrl_executable	5.260m	15.279ms	1	1	100.00
V2	partial_access	sram_ctrl_partial_access	7.490s	8.372ms	1	1	100.00
		sram_ctrl_partial_access_b2b	5.165m	105.009ms	1	1	100.00
V2	max_throughput	sram_ctrl_max_throughput	40.280s	1.420ms	1	1	100.00
		sram_ctrl_throughput_w_partial_write	36.710s	3.196ms	1	1	100.00
		sram_ctrl_throughput_w_readback	52.520s	1.882ms	1	1	100.00
V2	regwen	sram_ctrl_regwen	9.065m	13.329ms	1	1	100.00
V2	ram_cfg	sram_ctrl_ram_cfg	4.290s	354.906us	1	1	100.00
V2	stress_all	sram_ctrl_stress_all	44.600m	42.818ms	1	1	100.00
V2	alert_test	sram_ctrl_alert_test	1.060s	19.915us	1	1	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	4.360s	600.682us	1	1	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	4.360s	600.682us	1	1	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	0.750s	29.497us	1	1	100.00
		sram_ctrl_csr_rw	0.750s	40.224us	1	1	100.00
		sram_ctrl_csr_aliasing	0.710s	41.822us	1	1	100.00
		sram_ctrl_same_csr_outstanding	0.710s	50.454us	1	1	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	0.750s	29.497us	1	1	100.00
		sram_ctrl_csr_rw	0.750s	40.224us	1	1	100.00
		sram_ctrl_csr_aliasing	0.710s	41.822us	1	1	100.00
		sram_ctrl_same_csr_outstanding	0.710s	50.454us	1	1	100.00
V2		TOTAL			17	17	100.00
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	36.180s	7.307ms	1	1	100.00
V2S	tl_intg_err	sram_ctrl_sec_cm	0.940s	9.226us	0	1	0.00
		sram_ctrl_tl_intg_err	3.080s	695.094us	1	1	100.00
V2S	prim_count_check	sram_ctrl_sec_cm	0.940s	9.226us	0	1	0.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	3.080s	695.094us	1	1	100.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	9.065m	13.329ms	1	1	100.00
V2S	sec_cm_readback_config_regwen	sram_ctrl_regwen	9.065m	13.329ms	1	1	100.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	0.750s	40.224us	1	1	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	5.260m	15.279ms	1	1	100.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	5.260m	15.279ms	1	1	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	5.260m	15.279ms	1	1	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	6.850s	1.467ms	1	1	100.00
V2S	sec_cm_prim_ram_ctrl_mubi	sram_ctrl_mubi_enc_err	5.140s	719.242us	1	1	100.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	36.180s	7.307ms	1	1	100.00
V2S	sec_cm_mem_readback	sram_ctrl_readback_err	5.720s	679.033us	1	1	100.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	4.400s	1.385ms	1	1	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	4.400s	1.385ms	1	1	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	5.260m	15.279ms	1	1	100.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	0.940s	9.226us	0	1	0.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	6.850s	1.467ms	1	1	100.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	0.940s	9.226us	0	1	0.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	0.940s	9.226us	0	1	0.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	4.400s	1.385ms	1	1	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	0.940s	9.226us	0	1	0.00
V2S		TOTAL			4	5	80.00
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	6.510s	387.987us	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			30	31	96.77

Failure Buckets

• UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: * has 1 failures:
  • Test sram_ctrl_sec_cm has 1 failures.

    • 0.sram_ctrl_sec_cm.102154051032895843658726708727832893280307736432649548073612059131322512381337
      Line 96, in log /nightly/current_run/scratch/master/sram_ctrl_main-sim-vcs/0.sram_ctrl_sec_cm/latest/run.log

        UVM_ERROR @   9226265 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0
        UVM_INFO @   9226265 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---