SRAM_CTRL/RET Simulation Results

Monday October 06 2025 17:11:21 UTC

GitHub Revision: 0f6fcf0

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	1.410s	63.029us	1	1	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	0.910s	14.045us	1	1	100.00
V1	csr_rw	sram_ctrl_csr_rw	0.690s	20.388us	1	1	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	1.490s	85.646us	1	1	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	0.640s	38.975us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	1.190s	103.342us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	0.690s	20.388us	1	1	100.00
		sram_ctrl_csr_aliasing	0.640s	38.975us	1	1	100.00
V1	mem_walk	sram_ctrl_mem_walk	8.080s	2.822ms	1	1	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	2.310s	60.265us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	multiple_keys	sram_ctrl_multiple_keys	7.002m	14.600ms	1	1	100.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	2.604m	4.393ms	1	1	100.00
V2	bijection	sram_ctrl_bijection	16.580s	4.271ms	1	1	100.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	4.386m	10.938ms	1	1	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	3.160s	1.248ms	1	1	100.00
V2	executable	sram_ctrl_executable	9.626m	71.415ms	1	1	100.00
V2	partial_access	sram_ctrl_partial_access	2.170s	473.355us	1	1	100.00
		sram_ctrl_partial_access_b2b	4.924m	5.372ms	1	1	100.00
V2	max_throughput	sram_ctrl_max_throughput	16.940s	397.434us	1	1	100.00
		sram_ctrl_throughput_w_partial_write	53.140s	1.046ms	1	1	100.00
		sram_ctrl_throughput_w_readback	13.280s	326.713us	1	1	100.00
V2	regwen	sram_ctrl_regwen	2.170m	606.196us	1	1	100.00
V2	ram_cfg	sram_ctrl_ram_cfg	0.840s	352.889us	1	1	100.00
V2	stress_all	sram_ctrl_stress_all	31.454m	77.382ms	1	1	100.00
V2	alert_test	sram_ctrl_alert_test	0.860s	16.888us	1	1	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	3.490s	1.228ms	1	1	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	3.490s	1.228ms	1	1	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	0.910s	14.045us	1	1	100.00
		sram_ctrl_csr_rw	0.690s	20.388us	1	1	100.00
		sram_ctrl_csr_aliasing	0.640s	38.975us	1	1	100.00
		sram_ctrl_same_csr_outstanding	0.860s	25.250us	1	1	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	0.910s	14.045us	1	1	100.00
		sram_ctrl_csr_rw	0.690s	20.388us	1	1	100.00
		sram_ctrl_csr_aliasing	0.640s	38.975us	1	1	100.00
		sram_ctrl_same_csr_outstanding	0.860s	25.250us	1	1	100.00
V2		TOTAL			17	17	100.00
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	1.560s	330.598us	1	1	100.00
V2S	tl_intg_err	sram_ctrl_sec_cm	0.600s	7.462us	0	1	0.00
		sram_ctrl_tl_intg_err	1.470s	372.880us	1	1	100.00
V2S	prim_count_check	sram_ctrl_sec_cm	0.600s	7.462us	0	1	0.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	1.470s	372.880us	1	1	100.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	2.170m	606.196us	1	1	100.00
V2S	sec_cm_readback_config_regwen	sram_ctrl_regwen	2.170m	606.196us	1	1	100.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	0.690s	20.388us	1	1	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	9.626m	71.415ms	1	1	100.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	9.626m	71.415ms	1	1	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	9.626m	71.415ms	1	1	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	3.160s	1.248ms	1	1	100.00
V2S	sec_cm_prim_ram_ctrl_mubi	sram_ctrl_mubi_enc_err	1.020s	503.040us	1	1	100.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	1.560s	330.598us	1	1	100.00
V2S	sec_cm_mem_readback	sram_ctrl_readback_err	1.040s	34.773us	1	1	100.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	1.410s	63.029us	1	1	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	1.410s	63.029us	1	1	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	9.626m	71.415ms	1	1	100.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	0.600s	7.462us	0	1	0.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	3.160s	1.248ms	1	1	100.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	0.600s	7.462us	0	1	0.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	0.600s	7.462us	0	1	0.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	1.410s	63.029us	1	1	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	0.600s	7.462us	0	1	0.00
V2S		TOTAL			4	5	80.00
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	46.590s	1.424ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			30	31	96.77

Failure Buckets

• Offending '(d2h.d_opcode === (((curr_fwd ? curr_req.opcode : pend_req[d2h.d_source].opcode) == Get) ? AccessAckData : AccessAck))' has 1 failures:
  • Test sram_ctrl_sec_cm has 1 failures.

    • 0.sram_ctrl_sec_cm.94093381196706942164223320033366132838803095996647647678747028423031278859604
      Line 97, in log /nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/0.sram_ctrl_sec_cm/latest/run.log

            Offending '(d2h.d_opcode === (((curr_fwd ? curr_req.opcode : pend_req[d2h.d_source].opcode) == Get) ? AccessAckData : AccessAck))'
        "src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 293: tb.dut.tlul_assert_device_ram.gen_device.gen_d2h.respMustHaveReq_A: started at 3939568ps failed at 3939568ps
            Offending '(curr_fwd | pend_req[d2h.d_source].pend)'
        "src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 290: tb.dut.tlul_assert_device_ram.gen_device.gen_d2h.respOpcode_A: started at 3985023ps failed at 3985023ps
            Offending '(d2h.d_opcode === (((curr_fwd ? curr_req.opcode : pend_req[d2h.d_source].opcode) == Get) ? AccessAckData : AccessAck))'