SYSRST_CTRL Simulation Results

Monday October 06 2025 17:11:21 UTC

GitHub Revision: 0f6fcf0

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke sysrst_ctrl_smoke 1.480s 2.127ms 1 1 100.00
V1 input_output_inverted sysrst_ctrl_in_out_inverted 5.060s 2.455ms 1 1 100.00
V1 combo_detect_ec_rst sysrst_ctrl_combo_detect_ec_rst 4.370s 2.159ms 1 1 100.00
V1 combo_detect_ec_rst_with_pre_cond sysrst_ctrl_combo_detect_ec_rst_with_pre_cond 4.410s 2.309ms 1 1 100.00
V1 csr_hw_reset sysrst_ctrl_csr_hw_reset 6.850s 6.060ms 1 1 100.00
V1 csr_rw sysrst_ctrl_csr_rw 1.600s 2.060ms 1 1 100.00
V1 csr_bit_bash sysrst_ctrl_csr_bit_bash 1.556m 39.113ms 1 1 100.00
V1 csr_aliasing sysrst_ctrl_csr_aliasing 4.670s 2.330ms 1 1 100.00
V1 csr_mem_rw_with_rand_reset sysrst_ctrl_csr_mem_rw_with_rand_reset 4.470s 2.044ms 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr sysrst_ctrl_csr_rw 1.600s 2.060ms 1 1 100.00
sysrst_ctrl_csr_aliasing 4.670s 2.330ms 1 1 100.00
V1 TOTAL 9 9 100.00
V2 combo_detect sysrst_ctrl_combo_detect 1.133m 92.646ms 1 1 100.00
V2 combo_detect_with_pre_cond sysrst_ctrl_combo_detect_with_pre_cond 30.210s 60.515ms 1 1 100.00
V2 auto_block_key_outputs sysrst_ctrl_auto_blk_key_output 2.950s 3.677ms 1 1 100.00
V2 keyboard_input_triggered_interrupt sysrst_ctrl_edge_detect 2.400s 3.224ms 1 1 100.00
V2 pin_output_keyboard_inversion_control sysrst_ctrl_pin_override_test 5.540s 2.509ms 1 1 100.00
V2 pin_input_value_accessibility sysrst_ctrl_pin_access_test 4.480s 2.052ms 1 1 100.00
V2 ec_power_on_reset sysrst_ctrl_ec_pwr_on_rst 2.030s 4.406ms 1 1 100.00
V2 flash_write_protect_output sysrst_ctrl_flash_wr_prot_out 1.850s 2.625ms 1 1 100.00
V2 ultra_low_power_test sysrst_ctrl_ultra_low_pwr 6.200s 6.808ms 1 1 100.00
V2 sysrst_ctrl_feature_disable sysrst_ctrl_feature_disable 25.290s 33.324ms 1 1 100.00
V2 stress_all sysrst_ctrl_stress_all 1.305m 613.603ms 1 1 100.00
V2 alert_test sysrst_ctrl_alert_test 1.390s 2.034ms 1 1 100.00
V2 intr_test sysrst_ctrl_intr_test 4.280s 2.015ms 1 1 100.00
V2 tl_d_oob_addr_access sysrst_ctrl_tl_errors 3.630s 2.102ms 1 1 100.00
V2 tl_d_illegal_access sysrst_ctrl_tl_errors 3.630s 2.102ms 1 1 100.00
V2 tl_d_outstanding_access sysrst_ctrl_csr_hw_reset 6.850s 6.060ms 1 1 100.00
sysrst_ctrl_csr_rw 1.600s 2.060ms 1 1 100.00
sysrst_ctrl_csr_aliasing 4.670s 2.330ms 1 1 100.00
sysrst_ctrl_same_csr_outstanding 27.160s 10.265ms 1 1 100.00
V2 tl_d_partial_access sysrst_ctrl_csr_hw_reset 6.850s 6.060ms 1 1 100.00
sysrst_ctrl_csr_rw 1.600s 2.060ms 1 1 100.00
sysrst_ctrl_csr_aliasing 4.670s 2.330ms 1 1 100.00
sysrst_ctrl_same_csr_outstanding 27.160s 10.265ms 1 1 100.00
V2 TOTAL 15 15 100.00
V2S tl_intg_err sysrst_ctrl_sec_cm 18.850s 42.173ms 1 1 100.00
sysrst_ctrl_tl_intg_err 20.190s 43.031ms 1 1 100.00
V2S sec_cm_bus_integrity sysrst_ctrl_tl_intg_err 20.190s 43.031ms 1 1 100.00
V2S TOTAL 2 2 100.00
V3 stress_all_with_rand_reset sysrst_ctrl_stress_all_with_rand_reset 5.820s 10.762ms 1 1 100.00
V3 TOTAL 1 1 100.00
TOTAL 27 27 100.00