UART Simulation Results

Monday October 06 2025 17:11:21 UTC

GitHub Revision: 0f6fcf0

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	uart_smoke	0.920s	120.091us	1	1	100.00
V1	csr_hw_reset	uart_csr_hw_reset	0.750s	16.735us	1	1	100.00
V1	csr_rw	uart_csr_rw	0.780s	12.770us	1	1	100.00
V1	csr_bit_bash	uart_csr_bit_bash	1.920s	177.357us	1	1	100.00
V1	csr_aliasing	uart_csr_aliasing	0.960s	32.095us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	uart_csr_mem_rw_with_rand_reset	0.770s	45.782us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	uart_csr_rw	0.780s	12.770us	1	1	100.00
		uart_csr_aliasing	0.960s	32.095us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	base_random_seq	uart_tx_rx	20.780s	96.942ms	1	1	100.00
V2	parity	uart_smoke	0.920s	120.091us	1	1	100.00
		uart_tx_rx	20.780s	96.942ms	1	1	100.00
V2	parity_error	uart_intr	20.750s	24.621ms	1	1	100.00
		uart_rx_parity_err	3.249m	185.441ms	1	1	100.00
V2	watermark	uart_tx_rx	20.780s	96.942ms	1	1	100.00
		uart_intr	20.750s	24.621ms	1	1	100.00
V2	fifo_full	uart_fifo_full	27.240s	22.563ms	1	1	100.00
V2	fifo_overflow	uart_fifo_overflow	9.750s	17.089ms	1	1	100.00
V2	fifo_reset	uart_fifo_reset	42.220s	68.219ms	1	1	100.00
V2	rx_frame_err	uart_intr	20.750s	24.621ms	1	1	100.00
V2	rx_break_err	uart_intr	20.750s	24.621ms	1	1	100.00
V2	rx_timeout	uart_intr	20.750s	24.621ms	1	1	100.00
V2	perf	uart_perf	49.750s	5.313ms	1	1	100.00
V2	sys_loopback	uart_loopback	10.430s	8.557ms	1	1	100.00
V2	line_loopback	uart_loopback	10.430s	8.557ms	1	1	100.00
V2	rx_noise_filter	uart_noise_filter	5.940s	6.831ms	0	1	0.00
V2	rx_start_bit_filter	uart_rx_start_bit_filter	1.590s	3.132ms	1	1	100.00
V2	tx_overide	uart_tx_ovrd	1.450s	3.674ms	1	1	100.00
V2	rx_oversample	uart_rx_oversample	14.380s	2.501ms	1	1	100.00
V2	long_b2b_transfer	uart_long_xfer_wo_dly	1.279m	48.684ms	1	1	100.00
V2	stress_all	uart_stress_all	16.159m	60.296ms	1	1	100.00
V2	alert_test	uart_alert_test	0.780s	35.694us	1	1	100.00
V2	intr_test	uart_intr_test	0.740s	101.644us	1	1	100.00
V2	tl_d_oob_addr_access	uart_tl_errors	1.230s	38.985us	1	1	100.00
V2	tl_d_illegal_access	uart_tl_errors	1.230s	38.985us	1	1	100.00
V2	tl_d_outstanding_access	uart_csr_hw_reset	0.750s	16.735us	1	1	100.00
		uart_csr_rw	0.780s	12.770us	1	1	100.00
		uart_csr_aliasing	0.960s	32.095us	1	1	100.00
		uart_same_csr_outstanding	0.900s	24.668us	1	1	100.00
V2	tl_d_partial_access	uart_csr_hw_reset	0.750s	16.735us	1	1	100.00
		uart_csr_rw	0.780s	12.770us	1	1	100.00
		uart_csr_aliasing	0.960s	32.095us	1	1	100.00
		uart_same_csr_outstanding	0.900s	24.668us	1	1	100.00
V2		TOTAL			17	18	94.44
V2S	tl_intg_err	uart_sec_cm	0.950s	46.781us	1	1	100.00
		uart_tl_intg_err	1.370s	157.284us	1	1	100.00
V2S	sec_cm_bus_integrity	uart_tl_intg_err	1.370s	157.284us	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	stress_all_with_rand_reset	uart_stress_all_with_rand_reset	25.340s	12.151ms	0	1	0.00
V3		TOTAL			0	1	0.00
		TOTAL			25	27	92.59

Failure Buckets

• UVM_ERROR (uart_scoreboard.sv:445) [scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (* [*] vs * [*]) Interrupt: RxParityErr has 1 failures:

  • Test uart_noise_filter has 1 failures.

    • 0.uart_noise_filter.70087974565231766675187549484941052590557840201108041079752391868897123197198
      Line 71, in log /nightly/current_run/scratch/master/uart-sim-vcs/0.uart_noise_filter/latest/run.log

        UVM_ERROR @ 359592331 ps: (uart_scoreboard.sv:445) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (1 [0x1] vs 0 [0x0]) Interrupt: RxParityErr
        UVM_ERROR @ 359592331 ps: (uart_scoreboard.sv:447) [uvm_test_top.env.scoreboard] Check failed cfg.intr_vif.pins[i] === (intr_en[i] & intr_exp[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: RxParityErr
        UVM_ERROR @ 1036462736 ps: (uart_scoreboard.sv:377) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (0 [0x0] vs 1 [0x1]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 0
        UVM_ERROR @ 1036462736 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
        UVM_ERROR @ 1036462736 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1
      

• UVM_ERROR (uart_scoreboard.sv:501) scoreboard [scoreboard] rxlvl mismatch exp: * (+/-1), act: *, clk_pulses: * has 1 failures:

  • Test uart_stress_all_with_rand_reset has 1 failures.

    • 0.uart_stress_all_with_rand_reset.846204246560203457624524465888831774017233981254508892880137638201277361535
      Line 149, in log /nightly/current_run/scratch/master/uart-sim-vcs/0.uart_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 9534666371 ps: (uart_scoreboard.sv:501) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 0 (+/-1), act: 1,                                 clk_pulses: 0
        UVM_ERROR @ 9534786371 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty
        UVM_ERROR @ 9534866371 ps: (uart_scoreboard.sv:531) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 253 [0xfd]) reg name: uart_reg_block.rdata
        UVM_INFO @ 9913306371 ps: (cip_base_vseq__tl_errors.svh:290) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Running run_tl_errors_vseq 3/478
        UVM_ERROR @ 10046186371 ps: (uart_scoreboard.sv:501) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 0 (+/-1), act: 4,                                 clk_pulses: 0