CHIP Simulation Results

Monday October 06 2025 17:11:21 UTC

GitHub Revision: `0f6fcf0`

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	chip_sw_example_tests	chip_sw_example_flash	2.528m	3.237ms	1	1	100.00
		chip_sw_example_rom	1.329m	3.069ms	1	1	100.00
		chip_sw_example_manufacturer	3.081m	3.483ms	1	1	100.00
		chip_sw_example_concurrency	2.345m	2.746ms	1	1	100.00
V1	csr_hw_reset	chip_csr_hw_reset	3.420m	6.552ms	1	1	100.00
V1	csr_rw	chip_csr_rw	3.152m	3.905ms	1	1	100.00
V1	csr_bit_bash	chip_csr_bit_bash	9.888m	8.796ms	1	1	100.00
V1	csr_aliasing	chip_csr_aliasing	1.260h	34.192ms	1	1	100.00
V1	csr_mem_rw_with_rand_reset	chip_csr_mem_rw_with_rand_reset	50.880s	1.871ms	0	1	0.00
V1	regwen_csr_and_corresponding_lockable_csr	chip_csr_aliasing	1.260h	34.192ms	1	1	100.00
		chip_csr_rw	3.152m	3.905ms	1	1	100.00
V1	xbar_smoke	xbar_smoke	4.350s	37.814us	1	1	100.00
V1	chip_sw_gpio_out	chip_sw_gpio	4.825m	4.520ms	1	1	100.00
V1	chip_sw_gpio_in	chip_sw_gpio	4.825m	4.520ms	1	1	100.00
V1	chip_sw_gpio_irq	chip_sw_gpio	4.825m	4.520ms	1	1	100.00
V1	chip_sw_uart_tx_rx	chip_sw_uart_tx_rx	6.474m	4.404ms	1	1	100.00
V1	chip_sw_uart_rx_overflow	chip_sw_uart_tx_rx	6.474m	4.404ms	1	1	100.00
		chip_sw_uart_tx_rx_idx1	6.292m	4.364ms	1	1	100.00
		chip_sw_uart_tx_rx_idx2	5.389m	4.086ms	1	1	100.00
		chip_sw_uart_tx_rx_idx3	5.986m	3.722ms	1	1	100.00
V1	chip_sw_uart_baud_rate	chip_sw_uart_rand_baudrate	28.388m	13.267ms	1	1	100.00
V1	chip_sw_uart_tx_rx_alt_clk_freq	chip_sw_uart_tx_rx_alt_clk_freq	15.994m	8.428ms	1	1	100.00
		chip_sw_uart_tx_rx_alt_clk_freq_low_speed	18.693m	13.162ms	1	1	100.00
V1		TOTAL			17	18	94.44
V2	chip_pin_mux	chip_padctrl_attributes	2.259m	4.267ms	1	1	100.00
V2	chip_padctrl_attributes	chip_padctrl_attributes	2.259m	4.267ms	1	1	100.00
V2	chip_sw_sleep_pin_mio_dio_val	chip_sw_sleep_pin_mio_dio_val	3.335m	3.232ms	0	1	0.00
V2	chip_sw_sleep_pin_wake	chip_sw_sleep_pin_wake	2.371m	2.856ms	1	1	100.00
V2	chip_sw_sleep_pin_retention	chip_sw_sleep_pin_retention	3.964m	4.453ms	1	1	100.00
V2	chip_sw_tap_strap_sampling	chip_tap_straps_dev	9.050m	8.496ms	1	1	100.00
		chip_tap_straps_testunlock0	2.457m	3.798ms	1	1	100.00
		chip_tap_straps_rma	3.483m	4.591ms	1	1	100.00
		chip_tap_straps_prod	8.889m	8.719ms	1	1	100.00
V2	chip_sw_pattgen_ios	chip_sw_pattgen_ios	2.429m	2.704ms	1	1	100.00
V2	chip_sw_sleep_pwm_pulses	chip_sw_sleep_pwm_pulses	13.792m	9.625ms	1	1	100.00
V2	chip_sw_data_integrity	chip_sw_data_integrity_escalation	6.082m	6.341ms	1	1	100.00
V2	chip_sw_instruction_integrity	chip_sw_data_integrity_escalation	6.082m	6.341ms	1	1	100.00
V2	chip_sw_ast_clk_outputs	chip_sw_ast_clk_outputs	9.617m	7.016ms	1	1	100.00
V2	chip_sw_ast_clk_rst_inputs	chip_sw_ast_clk_rst_inputs	20.640m	14.673ms	0	1	0.00
V2	chip_sw_ast_sys_clk_jitter	chip_sw_flash_ctrl_ops_jitter_en	6.205m	4.106ms	1	1	100.00
		chip_sw_flash_ctrl_access_jitter_en	10.550m	5.973ms	1	1	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en	55.210m	18.827ms	1	1	100.00
		chip_sw_aes_enc_jitter_en	2.206m	3.197ms	1	1	100.00
		chip_sw_edn_entropy_reqs_jitter	9.948m	5.489ms	1	1	100.00
		chip_sw_hmac_enc_jitter_en	2.854m	2.770ms	1	1	100.00
		chip_sw_keymgr_key_derivation_jitter_en	20.905m	9.662ms	1	1	100.00
		chip_sw_kmac_mode_kmac_jitter_en	3.450m	2.929ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	5.224m	4.615ms	1	1	100.00
		chip_sw_clkmgr_jitter	2.641m	3.291ms	1	1	100.00
V2	chip_sw_ast_usb_clk_calib	chip_sw_usb_ast_clk_calib	3.516m	3.381ms	1	1	100.00
V2	chip_sw_sensor_ctrl_ast_alerts	chip_sw_sensor_ctrl_alert	8.565m	7.078ms	1	1	100.00
		chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	4.039m	5.368ms	1	1	100.00
V2	chip_sw_sensor_ctrl_ast_status	chip_sw_sensor_ctrl_status	1.698m	2.390ms	1	1	100.00
V2	chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	4.039m	5.368ms	1	1	100.00
V2	chip_sw_smoketest	chip_sw_flash_scrambling_smoketest	2.263m	2.417ms	1	1	100.00
		chip_sw_aes_smoketest	2.894m	2.919ms	1	1	100.00
		chip_sw_aon_timer_smoketest	3.494m	2.828ms	1	1	100.00
		chip_sw_clkmgr_smoketest	1.696m	2.327ms	1	1	100.00
		chip_sw_csrng_smoketest	2.812m	2.727ms	1	1	100.00
		chip_sw_entropy_src_smoketest	13.806m	6.634ms	1	1	100.00
		chip_sw_gpio_smoketest	2.891m	2.815ms	1	1	100.00
		chip_sw_hmac_smoketest	3.336m	3.707ms	1	1	100.00
		chip_sw_kmac_smoketest	3.783m	3.463ms	1	1	100.00
		chip_sw_otbn_smoketest	7.742m	4.870ms	1	1	100.00
		chip_sw_pwrmgr_smoketest	3.182m	6.129ms	1	1	100.00
		chip_sw_pwrmgr_usbdev_smoketest	4.206m	5.561ms	1	1	100.00
		chip_sw_rv_plic_smoketest	1.969m	3.225ms	1	1	100.00
		chip_sw_rv_timer_smoketest	2.834m	2.995ms	1	1	100.00
		chip_sw_rstmgr_smoketest	1.834m	2.513ms	1	1	100.00
		chip_sw_sram_ctrl_smoketest	1.878m	3.398ms	1	1	100.00
		chip_sw_uart_smoketest	2.047m	2.633ms	1	1	100.00
V2	chip_sw_otp_smoketest	chip_sw_otp_ctrl_smoketest	2.366m	3.059ms	1	1	100.00
V2	chip_sw_rom_functests	rom_keymgr_functest	4.413m	4.286ms	1	1	100.00
V2	chip_sw_boot	chip_sw_uart_tx_rx_bootstrap	2.195h	61.691ms	1	1	100.00
V2	chip_sw_secure_boot	rom_e2e_smoke	42.664m	15.133ms	1	1	100.00
V2	chip_sw_rom_raw_unlock	rom_raw_unlock	2.486m	5.230ms	1	1	100.00
V2	chip_sw_power_idle_load	chip_sw_power_idle_load	2.888m	3.592ms	0	1	0.00
V2	chip_sw_power_sleep_load	chip_sw_power_sleep_load	3.602m	3.403ms	0	1	0.00
V2	chip_sw_exit_test_unlocked_bootstrap	chip_sw_exit_test_unlocked_bootstrap	1.945h	53.778ms	1	1	100.00
V2	chip_sw_inject_scramble_seed	chip_sw_inject_scramble_seed	1.997h	57.096ms	1	1	100.00
V2	tl_d_oob_addr_access	chip_tl_errors	50.210s	2.198ms	0	1	0.00
V2	tl_d_illegal_access	chip_tl_errors	50.210s	2.198ms	0	1	0.00
V2	tl_d_outstanding_access	chip_csr_aliasing	1.260h	34.192ms	1	1	100.00
		chip_same_csr_outstanding	17.121m	15.591ms	1	1	100.00
		chip_csr_hw_reset	3.420m	6.552ms	1	1	100.00
		chip_csr_rw	3.152m	3.905ms	1	1	100.00
V2	tl_d_partial_access	chip_csr_aliasing	1.260h	34.192ms	1	1	100.00
		chip_same_csr_outstanding	17.121m	15.591ms	1	1	100.00
		chip_csr_hw_reset	3.420m	6.552ms	1	1	100.00
		chip_csr_rw	3.152m	3.905ms	1	1	100.00
V2	xbar_base_random_sequence	xbar_random	53.390s	2.170ms	1	1	100.00
V2	xbar_random_delay	xbar_smoke_zero_delays	4.370s	46.956us	1	1	100.00
		xbar_smoke_large_delays	40.480s	6.551ms	1	1	100.00
		xbar_smoke_slow_rsp	46.320s	5.468ms	1	1	100.00
		xbar_random_zero_delays	32.360s	642.345us	1	1	100.00
		xbar_random_large_delays	4.515m	45.913ms	1	1	100.00
		xbar_random_slow_rsp	3.143m	21.971ms	1	1	100.00
V2	xbar_unmapped_address	xbar_unmapped_addr	32.470s	1.158ms	1	1	100.00
		xbar_error_and_unmapped_addr	19.920s	770.763us	1	1	100.00
V2	xbar_error_cases	xbar_error_random	27.030s	1.519ms	1	1	100.00
		xbar_error_and_unmapped_addr	19.920s	770.763us	1	1	100.00
V2	xbar_all_access_same_device	xbar_access_same_device	49.100s	2.055ms	1	1	100.00
		xbar_access_same_device_slow_rsp	4.031m	27.745ms	1	1	100.00
V2	xbar_all_hosts_use_same_source_id	xbar_same_source	37.670s	2.093ms	1	1	100.00
V2	xbar_stress_all	xbar_stress_all	1.584m	5.041ms	1	1	100.00
		xbar_stress_all_with_error	6.079m	17.770ms	1	1	100.00
V2	xbar_stress_with_reset	xbar_stress_all_with_rand_reset	5.610m	3.361ms	1	1	100.00
		xbar_stress_all_with_reset_error	2.316m	1.299ms	1	1	100.00
V2	rom_e2e_smoke	rom_e2e_smoke	42.664m	15.133ms	1	1	100.00
V2	rom_e2e_shutdown_output	rom_e2e_shutdown_output	36.429m	25.563ms	1	1	100.00
V2	rom_e2e_shutdown_exception_c	rom_e2e_shutdown_exception_c	40.468m	14.522ms	1	1	100.00
V2	rom_e2e_boot_policy_valid	rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0	35.137m	13.711ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_dev	43.688m	16.319ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod	41.739m	16.053ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod_end	40.167m	14.946ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_rma	40.856m	16.919ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0	17.720s	10.340us	0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_dev	16.980s	10.240us	0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod	21.700s	10.240us	0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod_end	20.240s	10.180us	0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_rma	16.690s	10.340us	0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0	17.470s	10.200us	0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_dev	16.810s	10.380us	0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod	21.560s	10.400us	0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod_end	16.560s	10.140us	0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_rma	16.910s	10.200us	0	1	0.00
V2	rom_e2e_sigverify_always	rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0	16.360s	10.280us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_dev	16.170s	10.320us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod	19.040s	10.380us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod_end	19.010s	10.220us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_rma	17.500s	10.100us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0	16.150s	10.160us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_dev	17.000s	10.240us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod	16.780s	10.380us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod_end	22.050s	10.300us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_rma	17.460s	10.340us	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0	17.320s	10.260us	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_dev	16.980s	10.200us	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod	16.790s	10.220us	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod_end	16.550s	10.260us	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_rma	16.810s	10.180us	0	1	0.00
V2	rom_e2e_asm_init	rom_e2e_asm_init_test_unlocked0	31.279m	11.319ms	1	1	100.00
		rom_e2e_asm_init_dev	40.802m	15.781ms	1	1	100.00
		rom_e2e_asm_init_prod	41.620m	15.398ms	1	1	100.00
		rom_e2e_asm_init_prod_end	39.985m	16.233ms	1	1	100.00
		rom_e2e_asm_init_rma	38.091m	14.881ms	1	1	100.00
V2	rom_e2e_keymgr_init	rom_e2e_keymgr_init_rom_ext_meas	39.696m	15.103ms	1	1	100.00
		rom_e2e_keymgr_init_rom_ext_no_meas	38.924m	15.159ms	1	1	100.00
		rom_e2e_keymgr_init_rom_ext_invalid_meas	39.172m	14.600ms	1	1	100.00
V2	rom_e2e_static_critical	rom_e2e_static_critical	41.379m	17.000ms	1	1	100.00
V2	chip_sw_adc_ctrl_debug_cable_irq	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	49.060m	35.007ms	0	1	0.00
V2	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	49.060m	35.007ms	0	1	0.00
V2	chip_sw_aes_enc	chip_sw_aes_enc	2.154m	2.311ms	1	1	100.00
		chip_sw_aes_enc_jitter_en	2.206m	3.197ms	1	1	100.00
V2	chip_sw_aes_entropy	chip_sw_aes_entropy	2.171m	3.405ms	1	1	100.00
V2	chip_sw_aes_idle	chip_sw_aes_idle	1.709m	2.820ms	1	1	100.00
V2	chip_sw_aes_sideload	chip_sw_keymgr_sideload_aes	12.886m	7.677ms	1	1	100.00
V2	chip_sw_alert_handler_alerts	chip_sw_alert_test	2.645m	2.748ms	0	1	0.00
V2	chip_sw_alert_handler_escalations	chip_sw_alert_handler_escalation	4.766m	5.766ms	1	1	100.00
V2	chip_sw_all_escalation_resets	chip_sw_all_escalation_resets	6.440m	5.369ms	1	1	100.00
V2	chip_sw_alert_handler_irqs	chip_plic_all_irqs_0	9.050m	5.510ms	1	1	100.00
		chip_plic_all_irqs_10	4.188m	3.417ms	1	1	100.00
		chip_plic_all_irqs_20	5.781m	3.715ms	1	1	100.00
V2	chip_sw_alert_handler_entropy	chip_sw_alert_handler_entropy	2.823m	3.241ms	1	1	100.00
V2	chip_sw_alert_handler_crashdump	chip_sw_rstmgr_alert_info	14.894m	9.722ms	1	1	100.00
V2	chip_sw_alert_handler_ping_timeout	chip_sw_alert_handler_ping_timeout	4.478m	4.068ms	1	1	100.00
V2	chip_sw_alert_handler_lpg_sleep_mode_alerts	chip_sw_alert_handler_lpg_sleep_mode_alerts	2.216m	2.869ms	0	1	0.00
V2	chip_sw_alert_handler_lpg_sleep_mode_pings	chip_sw_alert_handler_lpg_sleep_mode_pings			0	1	0.00
V2	chip_sw_alert_handler_lpg_clock_off	chip_sw_alert_handler_lpg_clkoff	16.312m	7.093ms	1	1	100.00
V2	chip_sw_alert_handler_lpg_reset_toggle	chip_sw_alert_handler_lpg_reset_toggle	20.427m	8.978ms	1	1	100.00
V2	chip_sw_alert_handler_ping_ok	chip_sw_alert_handler_ping_ok	13.991m	7.800ms	1	1	100.00
V2	chip_sw_alert_handler_reverse_ping_in_deep_sleep	chip_sw_alert_handler_reverse_ping_in_deep_sleep	2.075h	255.290ms	1	1	100.00
V2	chip_sw_aon_timer_wakeup_irq	chip_sw_aon_timer_irq	4.661m	4.185ms	1	1	100.00
V2	chip_sw_aon_timer_sleep_wakeup	chip_sw_pwrmgr_smoketest	3.182m	6.129ms	1	1	100.00
V2	chip_sw_aon_timer_wdog_bark_irq	chip_sw_aon_timer_irq	4.661m	4.185ms	1	1	100.00
V2	chip_sw_aon_timer_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	9.361m	8.832ms	1	1	100.00
V2	chip_sw_aon_timer_sleep_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	9.361m	8.832ms	1	1	100.00
V2	chip_sw_aon_timer_sleep_wdog_sleep_pause	chip_sw_aon_timer_sleep_wdog_sleep_pause	4.595m	7.209ms	1	1	100.00
V2	chip_sw_aon_timer_wdog_lc_escalate	chip_sw_aon_timer_wdog_lc_escalate	5.543m	5.115ms	1	1	100.00
V2	chip_sw_clkmgr_idle_trans	chip_sw_otbn_randomness	10.138m	6.664ms	1	1	100.00
		chip_sw_aes_idle	1.709m	2.820ms	1	1	100.00
		chip_sw_hmac_enc_idle	2.803m	2.929ms	1	1	100.00
		chip_sw_kmac_idle	1.820m	3.077ms	1	1	100.00
V2	chip_sw_clkmgr_off_trans	chip_sw_clkmgr_off_aes_trans	5.098m	4.914ms	1	1	100.00
		chip_sw_clkmgr_off_hmac_trans	4.516m	4.068ms	1	1	100.00
		chip_sw_clkmgr_off_kmac_trans	3.558m	3.272ms	1	1	100.00
		chip_sw_clkmgr_off_otbn_trans	4.199m	4.327ms	1	1	100.00
V2	chip_sw_clkmgr_off_peri	chip_sw_clkmgr_off_peri	10.235m	9.951ms	1	1	100.00
V2	chip_sw_clkmgr_div	chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	6.211m	4.442ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	5.666m	4.468ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	6.483m	4.339ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	6.826m	4.811ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	5.753m	3.382ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	6.483m	4.288ms	1	1	100.00
		chip_sw_ast_clk_outputs	9.617m	7.016ms	1	1	100.00
V2	chip_sw_clkmgr_external_clk_src_for_lc	chip_sw_clkmgr_external_clk_src_for_lc	6.365m	6.927ms	1	1	100.00
V2	chip_sw_clkmgr_external_clk_src_for_sw	chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	6.483m	4.339ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	6.826m	4.811ms	1	1	100.00
V2	chip_sw_clkmgr_jitter	chip_sw_flash_ctrl_ops_jitter_en	6.205m	4.106ms	1	1	100.00
		chip_sw_flash_ctrl_access_jitter_en	10.550m	5.973ms	1	1	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en	55.210m	18.827ms	1	1	100.00
		chip_sw_aes_enc_jitter_en	2.206m	3.197ms	1	1	100.00
		chip_sw_edn_entropy_reqs_jitter	9.948m	5.489ms	1	1	100.00
		chip_sw_hmac_enc_jitter_en	2.854m	2.770ms	1	1	100.00
		chip_sw_keymgr_key_derivation_jitter_en	20.905m	9.662ms	1	1	100.00
		chip_sw_kmac_mode_kmac_jitter_en	3.450m	2.929ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	5.224m	4.615ms	1	1	100.00
		chip_sw_clkmgr_jitter	2.641m	3.291ms	1	1	100.00
V2	chip_sw_clkmgr_extended_range	chip_sw_clkmgr_jitter_reduced_freq	1.945m	2.763ms	1	1	100.00
		chip_sw_flash_ctrl_ops_jitter_en_reduced_freq	7.044m	4.625ms	1	1	100.00
		chip_sw_flash_ctrl_access_jitter_en_reduced_freq	10.894m	7.562ms	1	1	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq	51.071m	24.252ms	1	1	100.00
		chip_sw_aes_enc_jitter_en_reduced_freq	2.755m	3.229ms	1	1	100.00
		chip_sw_hmac_enc_jitter_en_reduced_freq	2.491m	3.342ms	1	1	100.00
		chip_sw_keymgr_key_derivation_jitter_en_reduced_freq	10.852m	8.424ms	1	1	100.00
		chip_sw_kmac_mode_kmac_jitter_en_reduced_freq	3.091m	3.163ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq	4.769m	4.171ms	1	1	100.00
		chip_sw_flash_init_reduced_freq	19.905m	24.058ms	1	1	100.00
		chip_sw_csrng_edn_concurrency_reduced_freq	34.245m	17.295ms	1	1	100.00
V2	chip_sw_clkmgr_deep_sleep_frequency	chip_sw_ast_clk_outputs	9.617m	7.016ms	1	1	100.00
V2	chip_sw_clkmgr_sleep_frequency	chip_sw_clkmgr_sleep_frequency	5.469m	4.775ms	1	1	100.00
V2	chip_sw_clkmgr_reset_frequency	chip_sw_clkmgr_reset_frequency	3.903m	3.442ms	1	1	100.00
V2	chip_sw_clkmgr_escalation_reset	chip_sw_all_escalation_resets	6.440m	5.369ms	1	1	100.00
V2	chip_sw_clkmgr_alert_handler_clock_enables	chip_sw_alert_handler_lpg_clkoff	16.312m	7.093ms	1	1	100.00
V2	chip_sw_csrng_edn_cmd	chip_sw_entropy_src_csrng	16.721m	7.528ms	1	1	100.00
V2	chip_sw_csrng_fuse_en_sw_app_read	chip_sw_csrng_fuse_en_sw_app_read_test	4.838m	4.368ms	1	1	100.00
V2	chip_sw_csrng_lc_hw_debug_en	chip_sw_csrng_lc_hw_debug_en_test	6.008m	5.386ms	1	1	100.00
V2	chip_sw_csrng_known_answer_tests	chip_sw_csrng_kat_test	2.245m	2.429ms	1	1	100.00
V2	chip_sw_edn_entropy_reqs	chip_sw_csrng_edn_concurrency	36.727m	13.267ms	1	1	100.00
		chip_sw_entropy_src_ast_rng_req	2.522m	3.014ms	1	1	100.00
		chip_sw_edn_entropy_reqs	14.369m	7.310ms	1	1	100.00
V2	chip_sw_entropy_src_ast_rng_req	chip_sw_entropy_src_ast_rng_req	2.522m	3.014ms	1	1	100.00
V2	chip_sw_entropy_src_csrng	chip_sw_entropy_src_csrng	16.721m	7.528ms	1	1	100.00
V2	chip_sw_entropy_src_known_answer_tests	chip_sw_entropy_src_kat_test	2.420m	3.044ms	1	1	100.00
V2	chip_sw_flash_init	chip_sw_flash_init	20.826m	21.347ms	1	1	100.00
V2	chip_sw_flash_host_access	chip_sw_flash_ctrl_access	9.755m	6.065ms	1	1	100.00
		chip_sw_flash_ctrl_access_jitter_en	10.550m	5.973ms	1	1	100.00
V2	chip_sw_flash_ctrl_ops	chip_sw_flash_ctrl_ops	5.032m	3.737ms	1	1	100.00
		chip_sw_flash_ctrl_ops_jitter_en	6.205m	4.106ms	1	1	100.00
V2	chip_sw_flash_rma_unlocked	chip_sw_flash_rma_unlocked	53.331m	42.121ms	1	1	100.00
V2	chip_sw_flash_scramble	chip_sw_flash_init	20.826m	21.347ms	1	1	100.00
V2	chip_sw_flash_idle_low_power	chip_sw_flash_ctrl_idle_low_power	3.652m	2.905ms	1	1	100.00
V2	chip_sw_flash_keymgr_seeds	chip_sw_keymgr_key_derivation	24.218m	11.210ms	1	1	100.00
V2	chip_sw_flash_lc_creator_seed_sw_rw_en	chip_sw_flash_ctrl_lc_rw_en	4.998m	4.490ms	1	1	100.00
V2	chip_sw_flash_creator_seed_wipe_on_rma	chip_sw_flash_rma_unlocked	53.331m	42.121ms	1	1	100.00
V2	chip_sw_flash_lc_owner_seed_sw_rw_en	chip_sw_flash_ctrl_lc_rw_en	4.998m	4.490ms	1	1	100.00
V2	chip_sw_flash_lc_iso_part_sw_rd_en	chip_sw_flash_ctrl_lc_rw_en	4.998m	4.490ms	1	1	100.00
V2	chip_sw_flash_lc_iso_part_sw_wr_en	chip_sw_flash_ctrl_lc_rw_en	4.998m	4.490ms	1	1	100.00
V2	chip_sw_flash_lc_seed_hw_rd_en	chip_sw_flash_ctrl_lc_rw_en	4.998m	4.490ms	1	1	100.00
V2	chip_sw_flash_lc_escalate_en	chip_sw_all_escalation_resets	6.440m	5.369ms	1	1	100.00
V2	chip_sw_flash_prim_tl_access	chip_prim_tl_access	1.625m	4.495ms	1	1	100.00
V2	chip_sw_flash_ctrl_clock_freqs	chip_sw_flash_ctrl_clock_freqs	8.475m	4.801ms	1	1	100.00
V2	chip_sw_flash_ctrl_escalation_reset	chip_sw_flash_crash_alert	6.459m	5.088ms	1	1	100.00
V2	chip_sw_flash_ctrl_write_clear	chip_sw_flash_crash_alert	6.459m	5.088ms	1	1	100.00
V2	chip_sw_hmac_enc	chip_sw_hmac_enc	3.182m	3.819ms	1	1	100.00
		chip_sw_hmac_enc_jitter_en	2.854m	2.770ms	1	1	100.00
V2	chip_sw_hmac_idle	chip_sw_hmac_enc_idle	2.803m	2.929ms	1	1	100.00
V2	chip_sw_hmac_all_configurations	chip_sw_hmac_oneshot	2.917m	3.053ms	0	1	0.00
V2	chip_sw_hmac_multistream_mode	chip_sw_hmac_multistream	5.701m	3.752ms	1	1	100.00
V2	chip_sw_i2c_host_tx_rx	chip_sw_i2c_host_tx_rx	6.224m	5.724ms	1	1	100.00
		chip_sw_i2c_host_tx_rx_idx1	6.636m	4.453ms	1	1	100.00
		chip_sw_i2c_host_tx_rx_idx2	7.390m	5.655ms	1	1	100.00
V2	chip_sw_i2c_device_tx_rx	chip_sw_i2c_device_tx_rx	4.185m	4.254ms	1	1	100.00
V2	chip_sw_keymgr_key_derivation	chip_sw_keymgr_key_derivation	24.218m	11.210ms	1	1	100.00
		chip_sw_keymgr_key_derivation_jitter_en	20.905m	9.662ms	1	1	100.00
V2	chip_sw_keymgr_sideload_kmac	chip_sw_keymgr_sideload_kmac	12.466m	6.651ms	1	1	100.00
V2	chip_sw_keymgr_sideload_aes	chip_sw_keymgr_sideload_aes	12.886m	7.677ms	1	1	100.00
V2	chip_sw_keymgr_sideload_otbn	chip_sw_keymgr_sideload_otbn	44.604m	13.875ms	1	1	100.00
V2	chip_sw_kmac_enc	chip_sw_kmac_mode_cshake	2.589m	2.482ms	1	1	100.00
		chip_sw_kmac_mode_kmac	2.987m	3.422ms	1	1	100.00
		chip_sw_kmac_mode_kmac_jitter_en	3.450m	2.929ms	1	1	100.00
V2	chip_sw_kmac_app_keymgr	chip_sw_keymgr_key_derivation	24.218m	11.210ms	1	1	100.00
V2	chip_sw_kmac_app_lc	chip_sw_lc_ctrl_transition	11.158m	9.598ms	1	1	100.00
V2	chip_sw_kmac_app_rom	chip_sw_kmac_app_rom	2.541m	3.041ms	1	1	100.00
V2	chip_sw_kmac_entropy	chip_sw_kmac_entropy	17.495m	7.896ms	1	1	100.00
V2	chip_sw_kmac_idle	chip_sw_kmac_idle	1.820m	3.077ms	1	1	100.00
V2	chip_sw_lc_ctrl_alert_handler_escalation	chip_sw_alert_handler_escalation	4.766m	5.766ms	1	1	100.00
V2	chip_sw_lc_ctrl_jtag_access	chip_tap_straps_dev	9.050m	8.496ms	1	1	100.00
		chip_tap_straps_rma	3.483m	4.591ms	1	1	100.00
		chip_tap_straps_prod	8.889m	8.719ms	1	1	100.00
V2	chip_sw_lc_ctrl_otp_hw_cfg0	chip_sw_lc_ctrl_otp_hw_cfg0	2.252m	2.705ms	1	1	100.00
V2	chip_sw_lc_ctrl_init	chip_sw_lc_ctrl_transition	11.158m	9.598ms	1	1	100.00
V2	chip_sw_lc_ctrl_transitions	chip_sw_lc_ctrl_transition	11.158m	9.598ms	1	1	100.00
V2	chip_sw_lc_ctrl_kmac_req	chip_sw_lc_ctrl_transition	11.158m	9.598ms	1	1	100.00
V2	chip_sw_lc_ctrl_key_div	chip_sw_keymgr_key_derivation_prod	21.908m	10.480ms	1	1	100.00
V2	chip_sw_lc_ctrl_broadcast	chip_sw_flash_ctrl_lc_rw_en	4.998m	4.490ms	1	1	100.00
		chip_sw_flash_rma_unlocked	53.331m	42.121ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_test_unlocked0	3.651m	3.573ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_dev	7.850m	5.519ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_prod	7.864m	5.368ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_rma	7.726m	6.607ms	1	1	100.00
		chip_sw_lc_ctrl_transition	11.158m	9.598ms	1	1	100.00
		chip_sw_keymgr_key_derivation	24.218m	11.210ms	1	1	100.00
		chip_sw_rom_ctrl_integrity_check	4.799m	9.506ms	1	1	100.00
		chip_sw_sram_ctrl_execution_main	6.765m	7.206ms	1	1	100.00
		chip_prim_tl_access	1.625m	4.495ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_lc	6.365m	6.927ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	6.211m	4.442ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	5.666m	4.468ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	6.483m	4.339ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	6.826m	4.811ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	5.753m	3.382ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	6.483m	4.288ms	1	1	100.00
		chip_tap_straps_dev	9.050m	8.496ms	1	1	100.00
		chip_tap_straps_rma	3.483m	4.591ms	1	1	100.00
		chip_tap_straps_prod	8.889m	8.719ms	1	1	100.00
		chip_rv_dm_lc_disabled	1.356m	3.474ms	0	1	0.00
V2	chip_lc_scrap	chip_sw_lc_ctrl_rma_to_scrap	3.383m	3.081ms	1	1	100.00
		chip_sw_lc_ctrl_raw_to_scrap	1.328m	2.980ms	1	1	100.00
		chip_sw_lc_ctrl_test_locked0_to_scrap	1.331m	2.616ms	1	1	100.00
		chip_sw_lc_ctrl_rand_to_scrap	3.289m	3.267ms	1	1	100.00
V2	chip_lc_test_locked	chip_sw_lc_walkthrough_testunlocks	25.805m	34.152ms	1	1	100.00
		chip_rv_dm_lc_disabled	1.356m	3.474ms	0	1	0.00
V2	chip_sw_lc_walkthrough	chip_sw_lc_walkthrough_dev	1.006h	49.447ms	1	1	100.00
		chip_sw_lc_walkthrough_prod	1.059h	49.632ms	1	1	100.00
		chip_sw_lc_walkthrough_prodend	9.009m	10.126ms	1	1	100.00
		chip_sw_lc_walkthrough_rma	1.082h	46.527ms	1	1	100.00
		chip_sw_lc_walkthrough_testunlocks	25.805m	34.152ms	1	1	100.00
V2	chip_sw_lc_ctrl_volatile_raw_unlock	chip_sw_lc_ctrl_volatile_raw_unlock	1.286m	2.955ms	1	1	100.00
		chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz	1.144m	2.036ms	1	1	100.00
		rom_volatile_raw_unlock	1.010m	2.177ms	1	1	100.00
V2	chip_sw_otbn_op	chip_sw_otbn_ecdsa_op_irq	54.819m	16.705ms	1	1	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en	55.210m	18.827ms	1	1	100.00
V2	chip_sw_otbn_rnd_entropy	chip_sw_otbn_randomness	10.138m	6.664ms	1	1	100.00
V2	chip_sw_otbn_urnd_entropy	chip_sw_otbn_randomness	10.138m	6.664ms	1	1	100.00
V2	chip_sw_otbn_idle	chip_sw_otbn_randomness	10.138m	6.664ms	1	1	100.00
V2	chip_sw_otbn_mem_scramble	chip_sw_otbn_mem_scramble	4.392m	3.341ms	1	1	100.00
V2	chip_otp_ctrl_init	chip_sw_lc_ctrl_transition	11.158m	9.598ms	1	1	100.00
V2	chip_sw_otp_ctrl_keys	chip_sw_flash_init	20.826m	21.347ms	1	1	100.00
		chip_sw_otbn_mem_scramble	4.392m	3.341ms	1	1	100.00
		chip_sw_keymgr_key_derivation	24.218m	11.210ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access	4.656m	4.917ms	1	1	100.00
		chip_sw_rv_core_ibex_icache_invalidate	2.873m	2.795ms	1	1	100.00
V2	chip_sw_otp_ctrl_entropy	chip_sw_flash_init	20.826m	21.347ms	1	1	100.00
		chip_sw_otbn_mem_scramble	4.392m	3.341ms	1	1	100.00
		chip_sw_keymgr_key_derivation	24.218m	11.210ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access	4.656m	4.917ms	1	1	100.00
		chip_sw_rv_core_ibex_icache_invalidate	2.873m	2.795ms	1	1	100.00
V2	chip_sw_otp_ctrl_program	chip_sw_lc_ctrl_transition	11.158m	9.598ms	1	1	100.00
V2	chip_sw_otp_ctrl_program_error	chip_sw_lc_ctrl_program_error	6.282m	6.065ms	1	1	100.00
V2	chip_sw_otp_ctrl_hw_cfg0	chip_sw_lc_ctrl_otp_hw_cfg0	2.252m	2.705ms	1	1	100.00
V2	chip_sw_otp_ctrl_lc_signals	chip_sw_otp_ctrl_lc_signals_test_unlocked0	3.651m	3.573ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_dev	7.850m	5.519ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_prod	7.864m	5.368ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_rma	7.726m	6.607ms	1	1	100.00
		chip_sw_lc_ctrl_transition	11.158m	9.598ms	1	1	100.00
		chip_prim_tl_access	1.625m	4.495ms	1	1	100.00
V2	chip_sw_otp_prim_tl_access	chip_prim_tl_access	1.625m	4.495ms	1	1	100.00
V2	chip_sw_otp_ctrl_dai_lock	chip_sw_otp_ctrl_dai_lock	16.909m	9.166ms	1	1	100.00
V2	chip_sw_pwrmgr_external_full_reset	chip_sw_pwrmgr_full_aon_reset	4.390m	7.063ms	1	1	100.00
V2	chip_sw_pwrmgr_random_sleep_all_wake_ups	chip_sw_pwrmgr_random_sleep_all_wake_ups	15.273m	24.132ms	1	1	100.00
V2	chip_sw_pwrmgr_normal_sleep_all_wake_ups	chip_sw_pwrmgr_normal_sleep_all_wake_ups	5.288m	7.455ms	1	1	100.00
V2	chip_sw_pwrmgr_deep_sleep_por_reset	chip_sw_pwrmgr_deep_sleep_por_reset	6.698m	9.793ms	1	1	100.00
V2	chip_sw_pwrmgr_normal_sleep_por_reset	chip_sw_pwrmgr_normal_sleep_por_reset	5.605m	6.520ms	1	1	100.00
V2	chip_sw_pwrmgr_deep_sleep_all_wake_ups	chip_sw_pwrmgr_deep_sleep_all_wake_ups	15.020m	25.814ms	1	1	100.00
V2	chip_sw_pwrmgr_deep_sleep_all_reset_reqs	chip_sw_pwrmgr_deep_sleep_all_reset_reqs	15.113m	15.109ms	1	1	100.00
		chip_sw_aon_timer_wdog_bite_reset	9.361m	8.832ms	1	1	100.00
V2	chip_sw_pwrmgr_normal_sleep_all_reset_reqs	chip_sw_pwrmgr_normal_sleep_all_reset_reqs	14.114m	9.672ms	1	1	100.00
V2	chip_sw_pwrmgr_wdog_reset	chip_sw_pwrmgr_wdog_reset	5.398m	4.411ms	1	1	100.00
V2	chip_sw_pwrmgr_aon_power_glitch_reset	chip_sw_pwrmgr_full_aon_reset	4.390m	7.063ms	1	1	100.00
V2	chip_sw_pwrmgr_main_power_glitch_reset	chip_sw_pwrmgr_main_power_glitch_reset	4.351m	4.162ms	1	1	100.00
V2	chip_sw_pwrmgr_random_sleep_power_glitch_reset	chip_sw_pwrmgr_random_sleep_power_glitch_reset	39.169m	33.226ms	1	1	100.00
V2	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	4.085m	5.985ms	1	1	100.00
V2	chip_sw_pwrmgr_sleep_power_glitch_reset	chip_sw_pwrmgr_sleep_power_glitch_reset	3.730m	5.156ms	1	1	100.00
V2	chip_sw_pwrmgr_random_sleep_all_reset_reqs	chip_sw_pwrmgr_random_sleep_all_reset_reqs	29.329m	28.251ms	1	1	100.00
V2	chip_sw_pwrmgr_sysrst_ctrl_reset	chip_sw_pwrmgr_sysrst_ctrl_reset	10.820m	7.393ms	1	1	100.00
		chip_sw_pwrmgr_all_reset_reqs	16.599m	10.112ms	1	1	100.00
V2	chip_sw_pwrmgr_b2b_sleep_reset_req	chip_sw_pwrmgr_b2b_sleep_reset_req	18.288m	25.404ms	1	1	100.00
V2	chip_sw_pwrmgr_sleep_disabled	chip_sw_pwrmgr_sleep_disabled	2.473m	3.385ms	1	1	100.00
V2	chip_sw_pwrmgr_escalation_reset	chip_sw_all_escalation_resets	6.440m	5.369ms	1	1	100.00
V2	chip_sw_rom_access	chip_sw_rom_ctrl_integrity_check	4.799m	9.506ms	1	1	100.00
V2	chip_sw_rom_ctrl_integrity_check	chip_sw_rom_ctrl_integrity_check	4.799m	9.506ms	1	1	100.00
V2	chip_sw_rstmgr_non_sys_reset_info	chip_sw_pwrmgr_all_reset_reqs	16.599m	10.112ms	1	1	100.00
		chip_sw_pwrmgr_random_sleep_all_reset_reqs	29.329m	28.251ms	1	1	100.00
		chip_sw_pwrmgr_wdog_reset	5.398m	4.411ms	1	1	100.00
		chip_sw_pwrmgr_smoketest	3.182m	6.129ms	1	1	100.00
V2	chip_sw_rstmgr_sys_reset_info	chip_rv_dm_ndm_reset_req	4.850m	4.103ms	1	1	100.00
V2	chip_sw_rstmgr_cpu_info	chip_sw_rstmgr_cpu_info	3.248m	3.616ms	0	1	0.00
V2	chip_sw_rstmgr_sw_req_reset	chip_sw_rstmgr_sw_req	4.371m	4.402ms	1	1	100.00
V2	chip_sw_rstmgr_alert_info	chip_sw_rstmgr_alert_info	14.894m	9.722ms	1	1	100.00
V2	chip_sw_rstmgr_sw_rst	chip_sw_rstmgr_sw_rst	2.830m	3.237ms	1	1	100.00
V2	chip_sw_rstmgr_escalation_reset	chip_sw_all_escalation_resets	6.440m	5.369ms	1	1	100.00
V2	chip_sw_rstmgr_alert_handler_reset_enables	chip_sw_alert_handler_lpg_reset_toggle	20.427m	8.978ms	1	1	100.00
V2	chip_sw_nmi_irq	chip_sw_rv_core_ibex_nmi_irq	7.592m	4.438ms	1	1	100.00
V2	chip_sw_rv_core_ibex_rnd	chip_sw_rv_core_ibex_rnd	8.526m	5.252ms	1	1	100.00
V2	chip_sw_rv_core_ibex_address_translation	chip_sw_rv_core_ibex_address_translation	3.010m	2.690ms	1	1	100.00
V2	chip_sw_rv_core_ibex_icache_scrambled_access	chip_sw_rv_core_ibex_icache_invalidate	2.873m	2.795ms	1	1	100.00
V2	chip_sw_rv_core_ibex_fault_dump	chip_sw_rstmgr_cpu_info	3.248m	3.616ms	0	1	0.00
V2	chip_sw_rv_core_ibex_double_fault	chip_sw_rstmgr_cpu_info	3.248m	3.616ms	0	1	0.00
V2	chip_jtag_csr_rw	chip_jtag_csr_rw	17.777m	17.333ms	1	1	100.00
V2	chip_jtag_mem_access	chip_jtag_mem_access	14.915m	13.274ms	1	1	100.00
V2	chip_rv_dm_ndm_reset_req	chip_rv_dm_ndm_reset_req	4.850m	4.103ms	1	1	100.00
V2	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	3.424m	3.842ms	1	1	100.00
V2	chip_rv_dm_access_after_wakeup	chip_sw_rv_dm_access_after_wakeup	4.000m	6.545ms	1	1	100.00
V2	chip_sw_rv_dm_jtag_tap_sel	chip_tap_straps_rma	3.483m	4.591ms	1	1	100.00
V2	chip_rv_dm_lc_disabled	chip_rv_dm_lc_disabled	1.356m	3.474ms	0	1	0.00
V2	chip_sw_plic_all_irqs	chip_plic_all_irqs_0	9.050m	5.510ms	1	1	100.00
		chip_plic_all_irqs_10	4.188m	3.417ms	1	1	100.00
		chip_plic_all_irqs_20	5.781m	3.715ms	1	1	100.00
V2	chip_sw_plic_sw_irq	chip_sw_plic_sw_irq	2.042m	2.755ms	1	1	100.00
V2	chip_sw_timer	chip_sw_rv_timer_irq	1.818m	2.228ms	1	1	100.00
V2	chip_sw_spi_device_flash_mode	rom_e2e_smoke	42.664m	15.133ms	1	1	100.00
V2	chip_sw_spi_device_pass_through	chip_sw_spi_device_pass_through	5.450m	5.879ms	1	1	100.00
V2	chip_sw_spi_device_pass_through_collision	chip_sw_spi_device_pass_through_collision	3.299m	3.249ms	0	1	0.00
V2	chip_sw_spi_device_tpm	chip_sw_spi_device_tpm	3.831m	3.136ms	1	1	100.00
V2	chip_sw_spi_host_tx_rx	chip_sw_spi_host_tx_rx	2.270m	3.220ms	1	1	100.00
V2	chip_sw_sram_scrambled_access	chip_sw_sram_ctrl_scrambled_access	4.656m	4.917ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	5.224m	4.615ms	1	1	100.00
V2	chip_sw_sleep_sram_ret_contents	chip_sw_sleep_sram_ret_contents_no_scramble	7.861m	9.148ms	1	1	100.00
		chip_sw_sleep_sram_ret_contents_scramble	4.837m	5.932ms	1	1	100.00
V2	chip_sw_sram_execution	chip_sw_sram_ctrl_execution_main	6.765m	7.206ms	1	1	100.00
V2	chip_sw_sram_lc_escalation	chip_sw_all_escalation_resets	6.440m	5.369ms	1	1	100.00
		chip_sw_data_integrity_escalation	6.082m	6.341ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_reset	chip_sw_pwrmgr_sysrst_ctrl_reset	10.820m	7.393ms	1	1	100.00
		chip_sw_sysrst_ctrl_reset	19.505m	24.737ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_inputs	chip_sw_sysrst_ctrl_inputs	2.062m	2.548ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_outputs	chip_sw_sysrst_ctrl_outputs	2.998m	4.029ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_in_irq	chip_sw_sysrst_ctrl_in_irq	5.073m	3.736ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_sleep_wakeup	chip_sw_sysrst_ctrl_reset	19.505m	24.737ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_sleep_reset	chip_sw_sysrst_ctrl_reset	19.505m	24.737ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_ec_rst_l	chip_sw_sysrst_ctrl_ec_rst_l	13.379m	11.812ms	0	1	0.00
V2	chip_sw_sysrst_ctrl_flash_wp_l	chip_sw_sysrst_ctrl_ec_rst_l	13.379m	11.812ms	0	1	0.00
V2	chip_sw_sysrst_ctrl_ulp_z3_wakeup	chip_sw_sysrst_ctrl_ulp_z3_wakeup	4.317m	5.252ms	1	1	100.00
		chip_sw_adc_ctrl_sleep_debug_cable_wakeup	49.060m	35.007ms	0	1	0.00
V2	chip_sw_usbdev_vbus	chip_sw_usbdev_vbus	1.791m	2.694ms	1	1	100.00
V2	chip_sw_usbdev_pullup	chip_sw_usbdev_pullup	2.578m	3.040ms	1	1	100.00
V2	chip_sw_usbdev_aon_pullup	chip_sw_usbdev_aon_pullup	5.082m	3.965ms	1	1	100.00
V2	chip_sw_usbdev_setup_rx	chip_sw_usbdev_setuprx	4.804m	4.381ms	1	1	100.00
V2	chip_sw_usbdev_config_host	chip_sw_usbdev_config_host	17.564m	8.066ms	1	1	100.00
V2	chip_sw_usbdev_pincfg	chip_sw_usbdev_pincfg	1.366h	30.771ms	1	1	100.00
V2	chip_sw_usbdev_tx_rx	chip_sw_usbdev_dpi	31.112m	12.189ms	1	1	100.00
V2	chip_sw_usbdev_toggle_restore	chip_sw_usbdev_toggle_restore	3.276m	3.040ms	1	1	100.00
V2		TOTAL			236	275	85.82
V2S	chip_sw_aes_masking_off	chip_sw_aes_masking_off	3.023m	3.231ms	1	1	100.00
V2S	chip_sw_rv_core_ibex_lockstep_glitch	chip_sw_rv_core_ibex_lockstep_glitch	2.319m	3.050ms	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	chip_sw_coremark	chip_sw_coremark	2.663h	71.842ms	1	1	100.00
V3	chip_sw_power_max_load	chip_sw_power_virus	15.707m	5.611ms	1	1	100.00
V3	rom_e2e_debug	rom_e2e_jtag_debug_test_unlocked0	3.154m	3.843ms	0	1	0.00
		rom_e2e_jtag_debug_dev	17.999m	10.551ms	1	1	100.00
		rom_e2e_jtag_debug_rma	18.633m	10.785ms	1	1	100.00
V3	rom_e2e_jtag_inject	rom_e2e_jtag_inject_test_unlocked0	3.301m	4.845ms	1	1	100.00
		rom_e2e_jtag_inject_dev	3.243m	3.301ms	1	1	100.00
		rom_e2e_jtag_inject_rma	3.176m	4.251ms	1	1	100.00
V3	rom_e2e_self_hash	rom_e2e_self_hash	12.531s		0	1	0.00
V3	chip_sw_clkmgr_jitter_cycle_measurements	chip_sw_clkmgr_jitter_frequency	7.924m	4.806ms	1	1	100.00
V3	chip_sw_edn_boot_mode	chip_sw_edn_boot_mode	4.626m	2.560ms	1	1	100.00
V3	chip_sw_edn_auto_mode	chip_sw_edn_auto_mode	10.539m	4.281ms	1	1	100.00
V3	chip_sw_edn_sw_mode	chip_sw_edn_sw_mode	25.507m	10.577ms	1	1	100.00
V3	chip_sw_edn_kat	chip_sw_edn_kat	3.658m	2.648ms	1	1	100.00
V3	chip_sw_flash_memory_protection	chip_sw_flash_ctrl_mem_protection	9.593m	5.234ms	1	1	100.00
V3	chip_sw_otp_ctrl_vendor_test_csr_access	chip_sw_otp_ctrl_vendor_test_csr_access	56.150s	2.557ms	1	1	100.00
V3	chip_sw_otp_ctrl_escalation	chip_sw_otp_ctrl_escalation	5.872m	5.521ms	1	1	100.00
V3	chip_sw_sensor_ctrl_deep_sleep_wake_up	chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up	4.698m	5.726ms	1	1	100.00
V3	chip_sw_pwrmgr_usb_clk_disabled_when_active	chip_sw_pwrmgr_usb_clk_disabled_when_active	4.963m	5.195ms	1	1	100.00
V3	chip_sw_all_resets	chip_sw_pwrmgr_all_reset_reqs	16.599m	10.112ms	1	1	100.00
V3	chip_rv_dm_perform_debug	rom_e2e_jtag_debug_test_unlocked0	3.154m	3.843ms	0	1	0.00
		rom_e2e_jtag_debug_dev	17.999m	10.551ms	1	1	100.00
		rom_e2e_jtag_debug_rma	18.633m	10.785ms	1	1	100.00
V3	chip_sw_rv_dm_access_after_hw_reset	chip_sw_rv_dm_access_after_escalation_reset	5.599m	5.489ms	1	1	100.00
V3	chip_sw_plic_alerts	chip_sw_all_escalation_resets	6.440m	5.369ms	1	1	100.00
V3	tick_configuration	chip_sw_rv_timer_systick_test	1.471h	37.436ms	1	1	100.00
V3	counter_wrap	chip_sw_rv_timer_systick_test	1.471h	37.436ms	1	1	100.00
V3	chip_sw_spi_device_output_when_disabled_or_sleeping	chip_sw_spi_device_pinmux_sleep_retention	2.904m	4.243ms	1	1	100.00
V3	chip_sw_uart_watermarks	chip_sw_uart_tx_rx	6.474m	4.404ms	1	1	100.00
V3	chip_sw_usbdev_stream	chip_sw_usbdev_stream	52.951m	19.507ms	1	1	100.00
V3		TOTAL			21	23	91.30
	Unmapped tests	chip_sival_flash_info_access	2.485m	2.949ms	1	1	100.00
		chip_sw_rstmgr_rst_cnsty_escalation	5.502m	4.981ms	1	1	100.00
		chip_sw_otp_ctrl_rot_auth_config	31.162m	23.427ms	0	1	0.00
		chip_sw_otp_ctrl_ecc_error_vendor_test	2.488m	3.277ms	1	1	100.00
		chip_sw_otp_ctrl_descrambling	3.355m	2.676ms	1	1	100.00
		chip_sw_pwrmgr_lowpower_cancel	3.058m	4.306ms	1	1	100.00
		chip_sw_pwrmgr_sleep_wake_5_bug	12.544s		0	1	0.00
		chip_sw_flash_ctrl_write_clear	2.446m	2.334ms	1	1	100.00
		TOTAL			282	326	86.50

Failure Buckets

UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_*.signed.*.scr.vmem could not be opened for r mode has 11 failures:
- Test rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0 has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0.70585670677579691697618672199275146547442536990844043688589617204334820867243
    Line 514, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0/latest/run.log
```
  UVM_FATAL @  10.200001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.200001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_bad_b_good_dev has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_bad_b_good_dev.63720869024780424477543393227242190107849794336304688884336029181720231748041
    Line 520, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_dev/latest/run.log
```
  UVM_FATAL @  10.380001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.380001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_bad_b_good_prod has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_bad_b_good_prod.25710680035523658929158316398819752636556132496128966055150375789981312491793
    Line 564, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod/latest/run.log
```
  UVM_FATAL @  10.400001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.400001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_bad_b_good_prod_end has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_bad_b_good_prod_end.72350468630636729252114231929677325585998048295593661745088373395063209500016
    Line 546, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod_end/latest/run.log
```
  UVM_FATAL @  10.140001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.140001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_bad_b_good_rma has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_bad_b_good_rma.5755735264457101100155416239846544242760218246709833767702712040570695603861
    Line 556, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_rma/latest/run.log
```
  UVM_FATAL @  10.200001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.200001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- ... and 6 more tests.
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_*.signed.*.scr.vmem could not be opened for r mode has 5 failures:
- Test rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0 has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0.58005706731561527998203335252063950779782419761268397891567052886110836058085
    Line 472, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0/latest/run.log
```
  UVM_FATAL @  10.340001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.340001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_good_b_bad_dev has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_good_b_bad_dev.95921671440193767106086793859459457825154130298631043389476451346608203307468
    Line 490, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_dev/latest/run.log
```
  UVM_FATAL @  10.240001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.240001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_good_b_bad_prod has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_good_b_bad_prod.3638392728916303116974220611981120716396997234918397558645100369316846810543
    Line 494, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod/latest/run.log
```
  UVM_FATAL @  10.240001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.240001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_good_b_bad_prod_end has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_good_b_bad_prod_end.17428733555079491263792887715065193771567036878898483483162546824606393322727
    Line 494, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod_end/latest/run.log
```
  UVM_FATAL @  10.180001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.180001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_good_b_bad_rma has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_good_b_bad_rma.42520647578627254674006373267235805941691022623516483571766888134042663802712
    Line 498, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_rma/latest/run.log
```
  UVM_FATAL @  10.340001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.340001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_*.signed.*.scr.vmem could not be opened for r mode has 3 failures:
- Test rom_e2e_sigverify_always_a_nothing_b_bad_prod has 1 failures.
  - 0.rom_e2e_sigverify_always_a_nothing_b_bad_prod.48361407375884621593017850702595197539518220681875501953380288489421272026790
    Line 494, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod/latest/run.log
```
  UVM_FATAL @  10.220001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.220001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_sigverify_always_a_nothing_b_bad_prod_end has 1 failures.
  - 0.rom_e2e_sigverify_always_a_nothing_b_bad_prod_end.94607890930308023323492988767121475330096850503424575955599912049670348625973
    Line 471, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod_end/latest/run.log
```
  UVM_FATAL @  10.260001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.260001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_sigverify_always_a_nothing_b_bad_rma has 1 failures.
  - 0.rom_e2e_sigverify_always_a_nothing_b_bad_rma.15228924080225838571244729359458185650631791544338838353686679739180929771895
    Line 521, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_rma/latest/run.log
```
  UVM_FATAL @  10.180001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.180001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

Job returned non-zero exit code has 2 failures:

Test chip_sw_pwrmgr_sleep_wake_5_bug has 1 failures.

0.chip_sw_pwrmgr_sleep_wake_5_bug.58118520515491476708152257626723397877405498190735769806180955299506908921133
Log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_pwrmgr_sleep_wake_5_bug/latest/run.log

  Computing main repo mapping:
  Loading:
  Loading: 0 packages loaded
  WARNING: Target pattern parsing failed.
  ERROR: Skipping '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD
  ERROR: no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD
  INFO: Elapsed time: 0.170s
  INFO: 0 processes.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

Test rom_e2e_self_hash has 1 failures.

0.rom_e2e_self_hash.109900513517171029485829405673246063550185507845150490032132347051922302028528
Log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_self_hash/latest/run.log

  Computing main repo mapping:
  Loading:
  Loading: 0 packages loaded
  WARNING: Target pattern parsing failed.
  ERROR: Skipping '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD
  ERROR: no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD
  INFO: Elapsed time: 0.160s
  INFO: 0 processes.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_test_key_*.signed.*.scr.vmem could not be opened for r mode has 2 failures:
- Test rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0 has 1 failures.
  - 0.rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0.88457500380636163364166369828877043778466488893701214644276015745503878222644
    Line 588, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0/latest/run.log
```
  UVM_FATAL @  10.280001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_test_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.280001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0 has 1 failures.
  - 0.rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0.19842754923639801586491107489821788545519028770740369034081541713011515894470
    Line 491, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0/latest/run.log
```
  UVM_FATAL @  10.160001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_test_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.160001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_dev_key_*.signed.*.scr.vmem could not be opened for r mode has 2 failures:
- Test rom_e2e_sigverify_always_a_bad_b_bad_dev has 1 failures.
  - 0.rom_e2e_sigverify_always_a_bad_b_bad_dev.61453505829959594924702414519727483216258974080646128419895231239135800975878
    Line 566, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_bad_dev/latest/run.log
```
  UVM_FATAL @  10.320001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_dev_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.320001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_sigverify_always_a_bad_b_nothing_dev has 1 failures.
  - 0.rom_e2e_sigverify_always_a_bad_b_nothing_dev.13992111685050071005480065131343503294095238261140128847774430613333538513087
    Line 516, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_nothing_dev/latest/run.log
```
  UVM_FATAL @  10.240001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_dev_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.240001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (chip_sw_sleep_pin_mio_dio_val_vseq.sv:92) [chip_sw_sleep_pin_mio_dio_val_vseq] Check failed cfg.chip_vif.mios_if.pins[i] === exp (* [*] vs *xz [z]) for MIO[*] has 1 failures:
- Test chip_sw_sleep_pin_mio_dio_val has 1 failures.
  - 0.chip_sw_sleep_pin_mio_dio_val.93653702870556505474274393373599633685628414614449078719316787253756799149397
    Line 632, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_sleep_pin_mio_dio_val/latest/run.log
```
  UVM_ERROR @ 3232.157000 us: (chip_sw_sleep_pin_mio_dio_val_vseq.sv:92) [uvm_test_top.env.virtual_sequencer.chip_sw_sleep_pin_mio_dio_val_vseq] Check failed cfg.chip_vif.mios_if.pins[i] === exp (0x0 [0] vs 0xz [z]) for MIO[30]
  UVM_INFO @ 3232.157000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:379)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty has 1 failures:
- Test chip_sw_spi_device_pass_through_collision has 1 failures.
  - 0.chip_sw_spi_device_pass_through_collision.97222595598221589487992825687363189025160544081533530541004829714082647463310
    Line 401, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_spi_device_pass_through_collision/latest/run.log
```
  UVM_ERROR @ 3248.776405 us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:379)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty
  UVM_INFO @ 3248.776405 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [otp_ctrl_rot_auth_config_test_sim_dv(sw/device/tests/otp_ctrl_rot_auth_config_test.c:22)] CHECK-STATUS-fail: @@@:* = ErrorError has 1 failures:
- Test chip_sw_otp_ctrl_rot_auth_config has 1 failures.
  - 0.chip_sw_otp_ctrl_rot_auth_config.31004757435262361098205557604594284632867166160687637852989175756879450048542
    Line 435, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_otp_ctrl_rot_auth_config/latest/run.log
```
  UVM_ERROR @ 23426.679627 us: (sw_logger_if.sv:526) [otp_ctrl_rot_auth_config_test_sim_dv(sw/device/tests/otp_ctrl_rot_auth_config_test.c:22)] CHECK-STATUS-fail: @@@:0 = ErrorError
  UVM_INFO @ 23426.679627 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@84948) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_sw_rstmgr_cpu_info has 1 failures.

0.chip_sw_rstmgr_cpu_info.83309562542038265015349364258823814377998914705408795193252586688515511017024
Line 414, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_rstmgr_cpu_info/latest/run.log

  UVM_ERROR @ 3616.391429 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (1 [0x1] vs 0 [0x0]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@84948) { a_addr: 'h8  a_data: 'h0  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h0  a_opcode: 'h0  a_user: 'h259aa  d_param: 'h0  d_source: 'h0  d_data: 'h0  d_size: 'h2  d_opcode: 'h0  d_error: 'h1  d_sink: 'h0  d_user: 'h1f2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 3616.391429 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (sw_logger_if.sv:526) [sysrst_ctrl_ec_rst_l_test_sim_dv(sw/device/tests/sim_dv/sysrst_ctrl_ec_rst_l_test.c:200)] CHECK-fail: rstmgr_reset_info == kDifRstmgrResetInfoPor has 1 failures:
- Test chip_sw_sysrst_ctrl_ec_rst_l has 1 failures.
  - 0.chip_sw_sysrst_ctrl_ec_rst_l.11791513616716766769816896261657500521675834145557172101411348627178694658120
    Line 402, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_sysrst_ctrl_ec_rst_l/latest/run.log
```
  UVM_ERROR @ 11812.254569 us: (sw_logger_if.sv:526) [sysrst_ctrl_ec_rst_l_test_sim_dv(sw/device/tests/sim_dv/sysrst_ctrl_ec_rst_l_test.c:200)] CHECK-fail: rstmgr_reset_info == kDifRstmgrResetInfoPor
  UVM_INFO @ 11812.254569 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (chip_sw_base_vseq.sv:317) virtual_sequencer [chip_sw_adc_ctrl_sleep_debug_cable_wakeup_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = * ns has 1 failures:
- Test chip_sw_adc_ctrl_sleep_debug_cable_wakeup has 1 failures.
  - 0.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.53435964649760242288609244699646287601585802005289129424999532606901003195787
    Line 414, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_adc_ctrl_sleep_debug_cable_wakeup/latest/run.log
```
  UVM_ERROR @ 35007.076027 us: (chip_sw_base_vseq.sv:317) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_adc_ctrl_sleep_debug_cable_wakeup_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = 18000000 ns

  UVM_INFO @ 35007.076027 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_test_sim_dv(hw/top_earlgrey/sw/autogen/tests/alert_test.c:322)] CHECK-fail: Expect alert *! has 1 failures:
- Test chip_sw_alert_test has 1 failures.
  - 0.chip_sw_alert_test.27554546313672423932907829653639160634640449510532847246233067480860295379311
    Line 390, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_alert_test/latest/run.log
```
  UVM_ERROR @ 2747.644225 us: (sw_logger_if.sv:526) [alert_test_sim_dv(hw/top_earlgrey/sw/autogen/tests/alert_test.c:322)] CHECK-fail: Expect alert 31!
  UVM_INFO @ 2747.644225 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0) has 1 failures:
- Test chip_sw_alert_handler_lpg_sleep_mode_alerts has 1 failures.
  - 0.chip_sw_alert_handler_lpg_sleep_mode_alerts.84322207338287590391612883752144958039332040616589975116270137601723248609
    Line 391, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log
```
  UVM_ERROR @ 2868.678944 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
  UVM_INFO @ 2868.678944 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Job timed out after * minutes has 1 failures:
- Test chip_sw_alert_handler_lpg_sleep_mode_pings has 1 failures.
  - 0.chip_sw_alert_handler_lpg_sleep_mode_pings.48759883514526852691366315393237275128332596426926845480641211034265299319846
    Log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_alert_handler_lpg_sleep_mode_pings/latest/run.log
```
  Job timed out after 240 minutes
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [hmac_functest_sim_dv(sw/device/tests/crypto/hmac_functest.c:79)] Finished test run_test_vector: *. has 1 failures:
- Test chip_sw_hmac_oneshot has 1 failures.
  - 0.chip_sw_hmac_oneshot.19874275772651743276349975954065340118306806818098595666715503503167730087077
    Line 400, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_hmac_oneshot/latest/run.log
```
  UVM_ERROR @ 3053.304026 us: (sw_logger_if.sv:526) [hmac_functest_sim_dv(sw/device/tests/crypto/hmac_functest.c:79)] Finished test run_test_vector: 8000534a.
  UVM_INFO @ 3053.304026 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@32264) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_tl_errors has 1 failures.

0.chip_tl_errors.56709140640215110692553897558161668030049270476323661750149928570407695163080
Line 214, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_tl_errors/latest/run.log

  UVM_ERROR @ 2198.402470 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@32264) { a_addr: 'h105e0  a_data: 'h295ff040  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h4  a_opcode: 'h4  a_user: 'h1924a  d_param: 'h0  d_source: 'h4  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 2198.402470 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (cip_base_vseq.sv:642) [chip_rv_dm_lc_disabled_vseq] Check failed masked_data == exp_data (* [*] vs * [*]) addr * read out mismatch has 1 failures:
- Test chip_rv_dm_lc_disabled has 1 failures.
  - 0.chip_rv_dm_lc_disabled.105814870098074050780957505837935818072198353863598050018940026330087744864027
    Line 213, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_rv_dm_lc_disabled/latest/run.log
```
  UVM_ERROR @ 3474.068520 us: (cip_base_vseq.sv:642) [uvm_test_top.env.virtual_sequencer.chip_rv_dm_lc_disabled_vseq] Check failed masked_data == exp_data (0 [0x0] vs 4294967295 [0xffffffff]) addr 0x10720 read out mismatch
  UVM_INFO @ 3474.068520 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (chip_sw_power_idle_load_vseq.sv:91) virtual_sequencer [chip_sw_power_idle_load_vseq] PWMCH* : pkt* Clock period is wrong. rcv : * exp : * has 1 failures:
- Test chip_sw_power_idle_load has 1 failures.
  - 0.chip_sw_power_idle_load.112659192660233350839915541630154770464119830800572938961449703134790247526598
    Line 395, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_power_idle_load/latest/run.log
```
  UVM_ERROR @ 3592.104500 us: (chip_sw_power_idle_load_vseq.sv:91) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_power_idle_load_vseq] PWMCH5 : pkt3 Clock period is wrong.  rcv : 2  exp : 32
  UVM_INFO @ 3592.104500 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (chip_sw_power_sleep_load_vseq.sv:114) virtual_sequencer [chip_sw_power_sleep_load_vseq] PWMCH* : pkt* Clock period is wrong. rcv : * exp : * has 1 failures:
- Test chip_sw_power_sleep_load has 1 failures.
  - 0.chip_sw_power_sleep_load.38146940742458587371465423654697754610253090916024475016128525289599173698624
    Line 403, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_power_sleep_load/latest/run.log
```
  UVM_ERROR @ 3403.337500 us: (chip_sw_power_sleep_load_vseq.sv:114) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_power_sleep_load_vseq] PWMCH5 : pkt3 Clock period is wrong.  rcv : 2  exp : 32
  UVM_INFO @ 3403.337500 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [ast_clk_rst_inputs_sim_dv(sw/device/tests/sim_dv/ast_clk_rst_inputs.c:147)] CHECK-fail: Recov alert not correctly observed in alert handler has 1 failures:
- Test chip_sw_ast_clk_rst_inputs has 1 failures.
  - 0.chip_sw_ast_clk_rst_inputs.33450680150544001216774688381297533672095603122598837436730360769085431939773
    Line 415, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_ast_clk_rst_inputs/latest/run.log
```
  UVM_ERROR @ 14672.543840 us: (sw_logger_if.sv:526) [ast_clk_rst_inputs_sim_dv(sw/device/tests/sim_dv/ast_clk_rst_inputs.c:147)] CHECK-fail: Recov alert not correctly observed in alert handler
  UVM_INFO @ 14672.543840 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_test_key_*.signed.*.scr.vmem could not be opened for r mode has 1 failures:
- Test rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0 has 1 failures.
  - 0.rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0.83972345904879279543628436438700368562920210490529633046168291473083871410902
    Line 502, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0/latest/run.log
```
  UVM_FATAL @  10.260001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_test_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.260001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_dev_key_*.signed.*.scr.vmem could not be opened for r mode has 1 failures:
- Test rom_e2e_sigverify_always_a_nothing_b_bad_dev has 1 failures.
  - 0.rom_e2e_sigverify_always_a_nothing_b_bad_dev.11197777620611812695814178392301350814071473454985496935946468511941571834540
    Line 497, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_dev/latest/run.log
```
  UVM_FATAL @  10.200001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_dev_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.200001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (jtag_rv_debugger.sv:784) [debugger] Index * appears to be out of bounds has 1 failures:
- Test rom_e2e_jtag_debug_test_unlocked0 has 1 failures.
  - 0.rom_e2e_jtag_debug_test_unlocked0.76368744518936009783623203628469992001204347913823912338199486803106085497296
    Line 419, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_jtag_debug_test_unlocked0/latest/run.log
```
  UVM_ERROR @ 3842.836520 us: (jtag_rv_debugger.sv:784) [debugger] Index 3 appears to be out of bounds
  UVM_INFO @ 3842.836520 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@31940) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_csr_mem_rw_with_rand_reset has 1 failures.

0.chip_csr_mem_rw_with_rand_reset.93270738881375208723492778145798029552071689347870313642693022233697120187404
Line 221, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_csr_mem_rw_with_rand_reset/latest/run.log

  UVM_ERROR @ 1871.111610 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@31940) { a_addr: 'h107f4  a_data: 'h3202abf5  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h25  a_opcode: 'h4  a_user: 'h1b106  d_param: 'h0  d_source: 'h25  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 1871.111610 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---