ADC_CTRL Simulation Results

Tuesday October 07 2025 19:21:11 UTC

GitHub Revision: 25151e0

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	adc_ctrl_smoke	5.200s	5.699ms	1	1	100.00
V1	csr_hw_reset	adc_ctrl_csr_hw_reset	1.010s	805.107us	1	1	100.00
V1	csr_rw	adc_ctrl_csr_rw	1.170s	462.343us	1	1	100.00
V1	csr_bit_bash	adc_ctrl_csr_bit_bash	37.910s	49.556ms	1	1	100.00
V1	csr_aliasing	adc_ctrl_csr_aliasing	3.430s	1.236ms	1	1	100.00
V1	csr_mem_rw_with_rand_reset	adc_ctrl_csr_mem_rw_with_rand_reset	1.380s	469.272us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	adc_ctrl_csr_rw	1.170s	462.343us	1	1	100.00
		adc_ctrl_csr_aliasing	3.430s	1.236ms	1	1	100.00
V1		TOTAL			6	6	100.00
V2	filters_polled	adc_ctrl_filters_polled	1.293m	168.303ms	1	1	100.00
V2	filters_polled_fixed	adc_ctrl_filters_polled_fixed	6.368m	326.306ms	1	1	100.00
V2	filters_interrupt	adc_ctrl_filters_interrupt	5.037m	162.807ms	1	1	100.00
V2	filters_interrupt_fixed	adc_ctrl_filters_interrupt_fixed	4.790m	162.166ms	1	1	100.00
V2	filters_wakeup	adc_ctrl_filters_wakeup	10.122m	333.242ms	1	1	100.00
V2	filters_wakeup_fixed	adc_ctrl_filters_wakeup_fixed	5.659m	200.523ms	1	1	100.00
V2	filters_both	adc_ctrl_filters_both	3.572m	192.934ms	1	1	100.00
V2	clock_gating	adc_ctrl_clock_gating	57.100s	161.387ms	1	1	100.00
V2	poweron_counter	adc_ctrl_poweron_counter	3.430s	4.832ms	1	1	100.00
V2	lowpower_counter	adc_ctrl_lowpower_counter	10.560s	42.395ms	1	1	100.00
V2	fsm_reset	adc_ctrl_fsm_reset	2.878m	91.030ms	1	1	100.00
V2	stress_all	adc_ctrl_stress_all	1.132m	138.912ms	1	1	100.00
V2	alert_test	adc_ctrl_alert_test	1.150s	424.527us	1	1	100.00
V2	intr_test	adc_ctrl_intr_test	1.280s	325.112us	1	1	100.00
V2	tl_d_oob_addr_access	adc_ctrl_tl_errors	3.550s	469.881us	1	1	100.00
V2	tl_d_illegal_access	adc_ctrl_tl_errors	3.550s	469.881us	1	1	100.00
V2	tl_d_outstanding_access	adc_ctrl_csr_hw_reset	1.010s	805.107us	1	1	100.00
		adc_ctrl_csr_rw	1.170s	462.343us	1	1	100.00
		adc_ctrl_csr_aliasing	3.430s	1.236ms	1	1	100.00
		adc_ctrl_same_csr_outstanding	8.260s	4.406ms	1	1	100.00
V2	tl_d_partial_access	adc_ctrl_csr_hw_reset	1.010s	805.107us	1	1	100.00
		adc_ctrl_csr_rw	1.170s	462.343us	1	1	100.00
		adc_ctrl_csr_aliasing	3.430s	1.236ms	1	1	100.00
		adc_ctrl_same_csr_outstanding	8.260s	4.406ms	1	1	100.00
V2		TOTAL			16	16	100.00
V2S	tl_intg_err	adc_ctrl_sec_cm	8.310s	4.126ms	1	1	100.00
		adc_ctrl_tl_intg_err	17.050s	8.123ms	1	1	100.00
V2S	sec_cm_bus_integrity	adc_ctrl_tl_intg_err	17.050s	8.123ms	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	stress_all_with_rand_reset	adc_ctrl_stress_all_with_rand_reset	10.190s	3.215ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			25	25	100.00