EDN Simulation Results

Tuesday October 07 2025 19:21:11 UTC

GitHub Revision: 25151e0

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	edn_smoke	1.020s	24.664us	1	1	100.00
V1	csr_hw_reset	edn_csr_hw_reset	0.860s	40.383us	1	1	100.00
V1	csr_rw	edn_csr_rw	0.850s	17.057us	1	1	100.00
V1	csr_bit_bash	edn_csr_bit_bash	1.520s	141.124us	1	1	100.00
V1	csr_aliasing	edn_csr_aliasing	1.060s	19.557us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	edn_csr_mem_rw_with_rand_reset	1.190s	173.904us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	edn_csr_rw	0.850s	17.057us	1	1	100.00
		edn_csr_aliasing	1.060s	19.557us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	firmware	edn_genbits	1.300s	96.940us	1	1	100.00
V2	csrng_commands	edn_genbits	1.300s	96.940us	1	1	100.00
V2	genbits	edn_genbits	1.300s	96.940us	1	1	100.00
V2	interrupts	edn_intr	0.900s	26.535us	1	1	100.00
V2	alerts	edn_alert	1.070s	25.571us	1	1	100.00
V2	errs	edn_err	0.770s	30.741us	1	1	100.00
V2	disable	edn_disable	0.890s	45.975us	1	1	100.00
		edn_disable_auto_req_mode	0.940s	120.131us	1	1	100.00
V2	stress_all	edn_stress_all	1.710s	768.981us	1	1	100.00
V2	intr_test	edn_intr_test	0.760s	23.220us	1	1	100.00
V2	alert_test	edn_alert_test	0.810s	25.607us	1	1	100.00
V2	tl_d_oob_addr_access	edn_tl_errors	2.440s	336.462us	1	1	100.00
V2	tl_d_illegal_access	edn_tl_errors	2.440s	336.462us	1	1	100.00
V2	tl_d_outstanding_access	edn_csr_hw_reset	0.860s	40.383us	1	1	100.00
		edn_csr_rw	0.850s	17.057us	1	1	100.00
		edn_csr_aliasing	1.060s	19.557us	1	1	100.00
		edn_same_csr_outstanding	0.890s	36.359us	1	1	100.00
V2	tl_d_partial_access	edn_csr_hw_reset	0.860s	40.383us	1	1	100.00
		edn_csr_rw	0.850s	17.057us	1	1	100.00
		edn_csr_aliasing	1.060s	19.557us	1	1	100.00
		edn_same_csr_outstanding	0.890s	36.359us	1	1	100.00
V2		TOTAL			11	11	100.00
V2S	tl_intg_err	edn_sec_cm	3.410s	3.138ms	1	1	100.00
		edn_tl_intg_err	1.890s	178.246us	1	1	100.00
V2S	sec_cm_config_regwen	edn_regwen	0.950s	32.062us	1	1	100.00
V2S	sec_cm_config_mubi	edn_alert	1.070s	25.571us	1	1	100.00
V2S	sec_cm_main_sm_fsm_sparse	edn_sec_cm	3.410s	3.138ms	1	1	100.00
V2S	sec_cm_ack_sm_fsm_sparse	edn_sec_cm	3.410s	3.138ms	1	1	100.00
V2S	sec_cm_fifo_ctr_redun	edn_sec_cm	3.410s	3.138ms	1	1	100.00
V2S	sec_cm_ctr_redun	edn_sec_cm	3.410s	3.138ms	1	1	100.00
V2S	sec_cm_main_sm_ctr_local_esc	edn_alert	1.070s	25.571us	1	1	100.00
		edn_sec_cm	3.410s	3.138ms	1	1	100.00
V2S	sec_cm_cs_rdata_bus_consistency	edn_alert	1.070s	25.571us	1	1	100.00
V2S	sec_cm_tile_link_bus_integrity	edn_tl_intg_err	1.890s	178.246us	1	1	100.00
V2S		TOTAL			3	3	100.00
V3	stress_all_with_rand_reset	edn_stress_all_with_rand_reset	27.430s	2.035ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			21	21	100.00