HMAC Simulation Results

Tuesday October 07 2025 19:21:11 UTC

GitHub Revision: 25151e0

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke hmac_smoke 3.970s 330.576us 1 1 100.00
V1 csr_hw_reset hmac_csr_hw_reset 1.010s 78.217us 1 1 100.00
V1 csr_rw hmac_csr_rw 0.790s 19.832us 1 1 100.00
V1 csr_bit_bash hmac_csr_bit_bash 11.030s 8.104ms 1 1 100.00
V1 csr_aliasing hmac_csr_aliasing 2.250s 116.478us 1 1 100.00
V1 csr_mem_rw_with_rand_reset hmac_csr_mem_rw_with_rand_reset 0.900s 13.594us 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr hmac_csr_rw 0.790s 19.832us 1 1 100.00
hmac_csr_aliasing 2.250s 116.478us 1 1 100.00
V1 TOTAL 6 6 100.00
V2 long_msg hmac_long_msg 1.210m 6.509ms 1 1 100.00
V2 back_pressure hmac_back_pressure 46.020s 4.023ms 1 1 100.00
V2 test_vectors hmac_test_sha256_vectors 7.730s 544.872us 1 1 100.00
hmac_test_sha384_vectors 6.641m 17.429ms 1 1 100.00
hmac_test_sha512_vectors 7.022m 13.948ms 1 1 100.00
hmac_test_hmac256_vectors 6.050s 194.574us 1 1 100.00
hmac_test_hmac384_vectors 7.230s 976.839us 1 1 100.00
hmac_test_hmac512_vectors 9.990s 337.288us 1 1 100.00
V2 burst_wr hmac_burst_wr 13.360s 1.317ms 1 1 100.00
V2 datapath_stress hmac_datapath_stress 1.730m 2.152ms 1 1 100.00
V2 error hmac_error 16.590s 526.304us 1 1 100.00
V2 wipe_secret hmac_wipe_secret 31.590s 812.158us 1 1 100.00
V2 save_and_restore hmac_smoke 3.970s 330.576us 1 1 100.00
hmac_long_msg 1.210m 6.509ms 1 1 100.00
hmac_back_pressure 46.020s 4.023ms 1 1 100.00
hmac_datapath_stress 1.730m 2.152ms 1 1 100.00
hmac_burst_wr 13.360s 1.317ms 1 1 100.00
hmac_stress_all 46.480s 5.555ms 1 1 100.00
V2 fifo_empty_status_interrupt hmac_smoke 3.970s 330.576us 1 1 100.00
hmac_long_msg 1.210m 6.509ms 1 1 100.00
hmac_back_pressure 46.020s 4.023ms 1 1 100.00
hmac_datapath_stress 1.730m 2.152ms 1 1 100.00
hmac_wipe_secret 31.590s 812.158us 1 1 100.00
hmac_test_sha256_vectors 7.730s 544.872us 1 1 100.00
hmac_test_sha384_vectors 6.641m 17.429ms 1 1 100.00
hmac_test_sha512_vectors 7.022m 13.948ms 1 1 100.00
hmac_test_hmac256_vectors 6.050s 194.574us 1 1 100.00
hmac_test_hmac384_vectors 7.230s 976.839us 1 1 100.00
hmac_test_hmac512_vectors 9.990s 337.288us 1 1 100.00
V2 wide_digest_configurable_key_length hmac_smoke 3.970s 330.576us 1 1 100.00
hmac_long_msg 1.210m 6.509ms 1 1 100.00
hmac_back_pressure 46.020s 4.023ms 1 1 100.00
hmac_datapath_stress 1.730m 2.152ms 1 1 100.00
hmac_burst_wr 13.360s 1.317ms 1 1 100.00
hmac_error 16.590s 526.304us 1 1 100.00
hmac_wipe_secret 31.590s 812.158us 1 1 100.00
hmac_test_sha256_vectors 7.730s 544.872us 1 1 100.00
hmac_test_sha384_vectors 6.641m 17.429ms 1 1 100.00
hmac_test_sha512_vectors 7.022m 13.948ms 1 1 100.00
hmac_test_hmac256_vectors 6.050s 194.574us 1 1 100.00
hmac_test_hmac384_vectors 7.230s 976.839us 1 1 100.00
hmac_test_hmac512_vectors 9.990s 337.288us 1 1 100.00
hmac_stress_all 46.480s 5.555ms 1 1 100.00
V2 stress_all hmac_stress_all 46.480s 5.555ms 1 1 100.00
V2 alert_test hmac_alert_test 0.610s 22.611us 1 1 100.00
V2 intr_test hmac_intr_test 0.680s 172.867us 1 1 100.00
V2 tl_d_oob_addr_access hmac_tl_errors 2.710s 70.686us 1 1 100.00
V2 tl_d_illegal_access hmac_tl_errors 2.710s 70.686us 1 1 100.00
V2 tl_d_outstanding_access hmac_csr_hw_reset 1.010s 78.217us 1 1 100.00
hmac_csr_rw 0.790s 19.832us 1 1 100.00
hmac_csr_aliasing 2.250s 116.478us 1 1 100.00
hmac_same_csr_outstanding 2.040s 164.398us 1 1 100.00
V2 tl_d_partial_access hmac_csr_hw_reset 1.010s 78.217us 1 1 100.00
hmac_csr_rw 0.790s 19.832us 1 1 100.00
hmac_csr_aliasing 2.250s 116.478us 1 1 100.00
hmac_same_csr_outstanding 2.040s 164.398us 1 1 100.00
V2 TOTAL 17 17 100.00
V2S tl_intg_err hmac_sec_cm 1.010s 96.878us 1 1 100.00
hmac_tl_intg_err 2.490s 110.519us 1 1 100.00
V2S sec_cm_bus_integrity hmac_tl_intg_err 2.490s 110.519us 1 1 100.00
V2S TOTAL 2 2 100.00
V3 write_config_and_secret_key_during_msg_wr hmac_smoke 3.970s 330.576us 1 1 100.00
V3 stress_reset hmac_stress_reset 2.880s 309.416us 1 1 100.00
V3 stress_all_with_rand_reset hmac_stress_all_with_rand_reset 1.143m 6.611ms 1 1 100.00
V3 TOTAL 2 2 100.00
Unmapped tests hmac_directed 1.010s 42.747us 1 1 100.00
TOTAL 28 28 100.00