I2C Simulation Results

Tuesday October 07 2025 19:21:11 UTC

GitHub Revision: `25151e0`

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	host_smoke	i2c_host_smoke	49.970s	1.536ms	1	1	100.00
V1	target_smoke	i2c_target_smoke	9.480s	2.678ms	1	1	100.00
V1	csr_hw_reset	i2c_csr_hw_reset	0.740s	81.765us	1	1	100.00
V1	csr_rw	i2c_csr_rw	1.080s	45.974us	1	1	100.00
V1	csr_bit_bash	i2c_csr_bit_bash	3.300s	118.409us	1	1	100.00
V1	csr_aliasing	i2c_csr_aliasing	1.250s	60.278us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	i2c_csr_mem_rw_with_rand_reset	1.300s	115.050us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	i2c_csr_rw	1.080s	45.974us	1	1	100.00
		i2c_csr_aliasing	1.250s	60.278us	1	1	100.00
V1		TOTAL			7	7	100.00
V2	host_error_intr	i2c_host_error_intr	0.820s	49.074us	0	1	0.00
V2	host_stress_all	i2c_host_stress_all	10.143m	56.609ms	0	1	0.00
V2	host_maxperf	i2c_host_perf			0	1	0.00
V2	host_override	i2c_host_override	0.630s	67.305us	1	1	100.00
V2	host_fifo_watermark	i2c_host_fifo_watermark	59.080s	16.422ms	1	1	100.00
V2	host_fifo_overflow	i2c_host_fifo_overflow	56.780s	11.901ms	1	1	100.00
V2	host_fifo_reset	i2c_host_fifo_reset_fmt	0.930s	198.710us	1	1	100.00
		i2c_host_fifo_fmt_empty	7.740s	540.585us	1	1	100.00
		i2c_host_fifo_reset_rx	5.550s	293.769us	1	1	100.00
V2	host_fifo_full	i2c_host_fifo_full	1.153m	38.475ms	1	1	100.00
V2	host_timeout	i2c_host_stretch_timeout	10.060s	832.065us	1	1	100.00
V2	i2c_host_mode_toggle	i2c_host_mode_toggle	1.240s	404.548us	0	1	0.00
V2	target_glitch	i2c_target_glitch	2.500s	937.931us	0	1	0.00
V2	target_stress_all	i2c_target_stress_all	2.049m	19.532ms	1	1	100.00
V2	target_maxperf	i2c_target_perf	2.860s	3.415ms	1	1	100.00
V2	target_fifo_empty	i2c_target_stress_rd	22.850s	3.216ms	1	1	100.00
		i2c_target_intr_smoke	3.370s	925.555us	1	1	100.00
V2	target_fifo_reset	i2c_target_fifo_reset_acq	1.440s	227.101us	1	1	100.00
		i2c_target_fifo_reset_tx	0.900s	130.646us	1	1	100.00
V2	target_fifo_full	i2c_target_stress_wr	1.854m	40.882ms	1	1	100.00
		i2c_target_stress_rd	22.850s	3.216ms	1	1	100.00
		i2c_target_intr_stress_wr	1.901m	11.700ms	1	1	100.00
V2	target_timeout	i2c_target_timeout	4.600s	1.150ms	1	1	100.00
V2	target_clock_stretch	i2c_target_stretch	9.660s	2.781ms	1	1	100.00
V2	bad_address	i2c_target_bad_addr	3.400s	2.147ms	1	1	100.00
V2	target_mode_glitch	i2c_target_hrst	18.250s	10.206ms	0	1	0.00
V2	target_fifo_watermark	i2c_target_fifo_watermarks_acq	1.890s	306.603us	1	1	100.00
		i2c_target_fifo_watermarks_tx	1.460s	468.062us	1	1	100.00
V2	host_mode_config_perf	i2c_host_perf			0	1	0.00
		i2c_host_perf_precise	1.580s	94.584us	1	1	100.00
V2	host_mode_clock_stretching	i2c_host_stretch_timeout	10.060s	832.065us	1	1	100.00
V2	target_mode_tx_stretch_ctrl	i2c_target_tx_stretch_ctrl	3.980s	322.807us	1	1	100.00
V2	target_mode_nack_generation	i2c_target_nack_acqfull	2.000s	1.790ms	1	1	100.00
		i2c_target_nack_acqfull_addr	2.420s	2.234ms	1	1	100.00
		i2c_target_nack_txstretch	1.200s	483.271us	1	1	100.00
V2	host_mode_halt_on_nak	i2c_host_may_nack	9.380s	625.709us	1	1	100.00
V2	target_mode_smbus_maxlen	i2c_target_smbus_maxlen	2.490s	1.145ms	1	1	100.00
V2	alert_test	i2c_alert_test	0.780s	33.464us	1	1	100.00
V2	intr_test	i2c_intr_test	0.770s	136.185us	1	1	100.00
V2	tl_d_oob_addr_access	i2c_tl_errors	2.190s	171.873us	1	1	100.00
V2	tl_d_illegal_access	i2c_tl_errors	2.190s	171.873us	1	1	100.00
V2	tl_d_outstanding_access	i2c_csr_hw_reset	0.740s	81.765us	1	1	100.00
		i2c_csr_rw	1.080s	45.974us	1	1	100.00
		i2c_csr_aliasing	1.250s	60.278us	1	1	100.00
		i2c_same_csr_outstanding	1.370s	53.369us	1	1	100.00
V2	tl_d_partial_access	i2c_csr_hw_reset	0.740s	81.765us	1	1	100.00
		i2c_csr_rw	1.080s	45.974us	1	1	100.00
		i2c_csr_aliasing	1.250s	60.278us	1	1	100.00
		i2c_same_csr_outstanding	1.370s	53.369us	1	1	100.00
V2		TOTAL			32	38	84.21
V2S	tl_intg_err	i2c_tl_intg_err	1.680s	370.217us	1	1	100.00
		i2c_sec_cm	1.060s	234.414us	1	1	100.00
V2S	sec_cm_bus_integrity	i2c_tl_intg_err	1.680s	370.217us	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	host_stress_all_with_rand_reset	i2c_host_stress_all_with_rand_reset	12.460s	1.314ms	0	1	0.00
V3	target_error_intr	i2c_target_unexp_stop	1.430s	1.810ms	0	1	0.00
V3	target_stress_all_with_rand_reset	i2c_target_stress_all_with_rand_reset	9.850s	2.973ms	0	1	0.00
V3		TOTAL			0	3	0.00
		TOTAL			41	50	82.00

Failure Buckets

UVM_ERROR sequencer [sequencer] Get_next_item called twice without item_done or get in between has 2 failures:
- Test i2c_host_error_intr has 1 failures.
  - 0.i2c_host_error_intr.24710102345832998912892529976573505171512451694111054132754769877334697843580
    Line 91, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_host_error_intr/latest/run.log
```
  UVM_ERROR @  49074454 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] Get_next_item called twice without item_done or get in between
  UVM_INFO @  49074454 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test i2c_target_stress_all_with_rand_reset has 1 failures.
  - 0.i2c_target_stress_all_with_rand_reset.9816348280348135051584267863892469077799952712104772779529847896795900602809
    Line 92, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_target_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 2973078621 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] Get_next_item called twice without item_done or get in between
  UVM_INFO @ 2973078621 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR (i2c_scoreboard.sv:716) [scoreboard] controller_mode_rd_obs_fifo item uncompared: has 2 failures:

Test i2c_host_stress_all has 1 failures.

0.i2c_host_stress_all.34877572535269194877943189045601150367437338998741860052439919073784192571681
Line 145, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_host_stress_all/latest/run.log

  UVM_ERROR @ 56609224660 ps: (i2c_scoreboard.sv:716) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared:
  ----------------------------------------------------
  Name            Type                Size  Value
  ----------------------------------------------------
  mon_dut_item    i2c_item            -     @16749685

Test i2c_host_mode_toggle has 1 failures.

0.i2c_host_mode_toggle.95880783405449795203095401758868519498503608533835636229151313872272714770529
Line 82, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_host_mode_toggle/latest/run.log

  UVM_ERROR @ 404548497 ps: (i2c_scoreboard.sv:716) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared:
  ----------------------------------------------------
  Name            Type                Size  Value
  ----------------------------------------------------
  mon_dut_item    i2c_item            -     @17754

Job timed out after * minutes has 1 failures:
- Test i2c_host_perf has 1 failures.
  - 0.i2c_host_perf.79240865941608674176221860281656159431536966722917985083702526845513232791307
    Log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_host_perf/latest/run.log
```
  Job timed out after 60 minutes
```
UVM_ERROR sequencer [sequencer] get_next_item/try_next_item called twice without item_done or get in between has 1 failures:
- Test i2c_target_glitch has 1 failures.
  - 0.i2c_target_glitch.86106802940739443501302994651337200199678101625067890384595611215722639247260
    Line 81, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_target_glitch/latest/run.log
```
  UVM_ERROR @ 937931000 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] get_next_item/try_next_item called twice without item_done or get in between
  UVM_INFO @ 937931000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (i2c_scoreboard.sv:682) [scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (* [*] vs * [*]) has 1 failures:
- Test i2c_target_unexp_stop has 1 failures.
  - 0.i2c_target_unexp_stop.51162276509258533905055325266214259210208951183993943952136465350387634216806
    Line 75, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_target_unexp_stop/latest/run.log
```
  UVM_ERROR @ 1810493294 ps: (i2c_scoreboard.sv:682) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 217 [0xd9])
  UVM_INFO @ 1810493294 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred! has 1 failures:
- Test i2c_target_hrst has 1 failures.
  - 0.i2c_target_hrst.43140357296855960658385556351520976090225678461338907823834681085364099081599
    Line 76, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_target_hrst/latest/run.log
```
  UVM_FATAL @ 10206470004 ps: (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred!
  UVM_INFO @ 10206470004 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (cip_base_vseq.sv:1229) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:
- Test i2c_host_stress_all_with_rand_reset has 1 failures.
  - 0.i2c_host_stress_all_with_rand_reset.2990512235568775507162088191179276735816296380156914446318928391523018959593
    Line 119, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_host_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 1313717034 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 1313717034 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```