KEYMGR Simulation Results

Tuesday October 07 2025 19:21:11 UTC

GitHub Revision: 25151e0

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke keymgr_smoke 1.650s 41.601us 1 1 100.00
V1 random keymgr_random 17.630s 1.996ms 1 1 100.00
V1 csr_hw_reset keymgr_csr_hw_reset 0.760s 18.030us 1 1 100.00
V1 csr_rw keymgr_csr_rw 0.920s 58.286us 1 1 100.00
V1 csr_bit_bash keymgr_csr_bit_bash 12.850s 5.174ms 1 1 100.00
V1 csr_aliasing keymgr_csr_aliasing 5.350s 262.064us 1 1 100.00
V1 csr_mem_rw_with_rand_reset keymgr_csr_mem_rw_with_rand_reset 1.530s 31.770us 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr keymgr_csr_rw 0.920s 58.286us 1 1 100.00
keymgr_csr_aliasing 5.350s 262.064us 1 1 100.00
V1 TOTAL 7 7 100.00
V2 cfgen_during_op keymgr_cfg_regwen 4.560s 221.503us 1 1 100.00
V2 sideload keymgr_sideload 1.970s 58.972us 1 1 100.00
keymgr_sideload_kmac 2.470s 368.531us 1 1 100.00
keymgr_sideload_aes 3.560s 282.576us 1 1 100.00
keymgr_sideload_otbn 11.070s 4.599ms 1 1 100.00
V2 direct_to_disabled_state keymgr_direct_to_disabled 1.760s 135.576us 1 1 100.00
V2 lc_disable keymgr_lc_disable 1.720s 139.685us 1 1 100.00
V2 kmac_error_response keymgr_kmac_rsp_err 2.130s 71.902us 1 1 100.00
V2 invalid_sw_input keymgr_sw_invalid_input 2.570s 292.347us 1 1 100.00
V2 invalid_hw_input keymgr_hwsw_invalid_input 2.350s 107.070us 1 1 100.00
V2 sync_async_fault_cross keymgr_sync_async_fault_cross 1.600s 32.627us 1 1 100.00
V2 stress_all keymgr_stress_all 23.850s 3.187ms 1 1 100.00
V2 intr_test keymgr_intr_test 0.750s 43.186us 1 1 100.00
V2 alert_test keymgr_alert_test 0.710s 85.061us 1 1 100.00
V2 tl_d_oob_addr_access keymgr_tl_errors 1.420s 385.521us 1 1 100.00
V2 tl_d_illegal_access keymgr_tl_errors 1.420s 385.521us 1 1 100.00
V2 tl_d_outstanding_access keymgr_csr_hw_reset 0.760s 18.030us 1 1 100.00
keymgr_csr_rw 0.920s 58.286us 1 1 100.00
keymgr_csr_aliasing 5.350s 262.064us 1 1 100.00
keymgr_same_csr_outstanding 3.080s 119.113us 1 1 100.00
V2 tl_d_partial_access keymgr_csr_hw_reset 0.760s 18.030us 1 1 100.00
keymgr_csr_rw 0.920s 58.286us 1 1 100.00
keymgr_csr_aliasing 5.350s 262.064us 1 1 100.00
keymgr_same_csr_outstanding 3.080s 119.113us 1 1 100.00
V2 TOTAL 16 16 100.00
V2S sec_cm_additional_check keymgr_sec_cm 3.480s 823.655us 1 1 100.00
V2S tl_intg_err keymgr_sec_cm 3.480s 823.655us 1 1 100.00
keymgr_tl_intg_err 2.960s 122.608us 1 1 100.00
V2S shadow_reg_update_error keymgr_shadow_reg_errors 1.870s 67.824us 1 1 100.00
V2S shadow_reg_read_clear_staged_value keymgr_shadow_reg_errors 1.870s 67.824us 1 1 100.00
V2S shadow_reg_storage_error keymgr_shadow_reg_errors 1.870s 67.824us 1 1 100.00
V2S shadowed_reset_glitch keymgr_shadow_reg_errors 1.870s 67.824us 1 1 100.00
V2S shadow_reg_update_error_with_csr_rw keymgr_shadow_reg_errors_with_csr_rw 8.010s 1.184ms 1 1 100.00
V2S prim_count_check keymgr_sec_cm 3.480s 823.655us 1 1 100.00
V2S prim_fsm_check keymgr_sec_cm 3.480s 823.655us 1 1 100.00
V2S sec_cm_bus_integrity keymgr_tl_intg_err 2.960s 122.608us 1 1 100.00
V2S sec_cm_config_shadow keymgr_shadow_reg_errors 1.870s 67.824us 1 1 100.00
V2S sec_cm_op_config_regwen keymgr_cfg_regwen 4.560s 221.503us 1 1 100.00
V2S sec_cm_reseed_config_regwen keymgr_random 17.630s 1.996ms 1 1 100.00
keymgr_csr_rw 0.920s 58.286us 1 1 100.00
V2S sec_cm_sw_binding_config_regwen keymgr_random 17.630s 1.996ms 1 1 100.00
keymgr_csr_rw 0.920s 58.286us 1 1 100.00
V2S sec_cm_max_key_ver_config_regwen keymgr_random 17.630s 1.996ms 1 1 100.00
keymgr_csr_rw 0.920s 58.286us 1 1 100.00
V2S sec_cm_lc_ctrl_intersig_mubi keymgr_lc_disable 1.720s 139.685us 1 1 100.00
V2S sec_cm_constants_consistency keymgr_hwsw_invalid_input 2.350s 107.070us 1 1 100.00
V2S sec_cm_intersig_consistency keymgr_hwsw_invalid_input 2.350s 107.070us 1 1 100.00
V2S sec_cm_hw_key_sw_noaccess keymgr_random 17.630s 1.996ms 1 1 100.00
V2S sec_cm_output_keys_ctrl_redun keymgr_sideload_protect 1.510s 70.280us 1 1 100.00
V2S sec_cm_ctrl_fsm_sparse keymgr_sec_cm 3.480s 823.655us 1 1 100.00
V2S sec_cm_data_fsm_sparse keymgr_sec_cm 3.480s 823.655us 1 1 100.00
V2S sec_cm_ctrl_fsm_local_esc keymgr_sec_cm 3.480s 823.655us 1 1 100.00
V2S sec_cm_ctrl_fsm_consistency keymgr_custom_cm 2.500s 377.937us 1 1 100.00
V2S sec_cm_ctrl_fsm_global_esc keymgr_lc_disable 1.720s 139.685us 1 1 100.00
V2S sec_cm_ctrl_ctr_redun keymgr_sec_cm 3.480s 823.655us 1 1 100.00
V2S sec_cm_kmac_if_fsm_sparse keymgr_sec_cm 3.480s 823.655us 1 1 100.00
V2S sec_cm_kmac_if_ctr_redun keymgr_sec_cm 3.480s 823.655us 1 1 100.00
V2S sec_cm_kmac_if_cmd_ctrl_consistency keymgr_custom_cm 2.500s 377.937us 1 1 100.00
V2S sec_cm_kmac_if_done_ctrl_consistency keymgr_custom_cm 2.500s 377.937us 1 1 100.00
V2S sec_cm_reseed_ctr_redun keymgr_sec_cm 3.480s 823.655us 1 1 100.00
V2S sec_cm_side_load_sel_ctrl_consistency keymgr_custom_cm 2.500s 377.937us 1 1 100.00
V2S sec_cm_sideload_ctrl_fsm_sparse keymgr_sec_cm 3.480s 823.655us 1 1 100.00
V2S sec_cm_ctrl_key_integrity keymgr_custom_cm 2.500s 377.937us 1 1 100.00
V2S TOTAL 6 6 100.00
V3 stress_all_with_rand_reset keymgr_stress_all_with_rand_reset 12.290s 729.523us 1 1 100.00
V3 TOTAL 1 1 100.00
TOTAL 30 30 100.00