| V1 |
smoke |
kmac_smoke |
10.040s |
622.035us |
1 |
1 |
100.00 |
| V1 |
csr_hw_reset |
kmac_csr_hw_reset |
0.970s |
36.922us |
1 |
1 |
100.00 |
| V1 |
csr_rw |
kmac_csr_rw |
1.200s |
29.532us |
1 |
1 |
100.00 |
| V1 |
csr_bit_bash |
kmac_csr_bit_bash |
5.600s |
156.726us |
1 |
1 |
100.00 |
| V1 |
csr_aliasing |
kmac_csr_aliasing |
5.410s |
136.648us |
1 |
1 |
100.00 |
| V1 |
csr_mem_rw_with_rand_reset |
kmac_csr_mem_rw_with_rand_reset |
2.960s |
142.388us |
1 |
1 |
100.00 |
| V1 |
regwen_csr_and_corresponding_lockable_csr |
kmac_csr_rw |
1.200s |
29.532us |
1 |
1 |
100.00 |
|
|
kmac_csr_aliasing |
5.410s |
136.648us |
1 |
1 |
100.00 |
| V1 |
mem_walk |
kmac_mem_walk |
0.850s |
13.521us |
1 |
1 |
100.00 |
| V1 |
mem_partial_access |
kmac_mem_partial_access |
1.210s |
41.207us |
1 |
1 |
100.00 |
| V1 |
|
TOTAL |
|
|
8 |
8 |
100.00 |
| V2 |
long_msg_and_output |
kmac_long_msg_and_output |
19.780m |
56.671ms |
1 |
1 |
100.00 |
| V2 |
burst_write |
kmac_burst_write |
8.743m |
17.418ms |
1 |
1 |
100.00 |
| V2 |
test_vectors |
kmac_test_vectors_sha3_224 |
33.291m |
313.633ms |
1 |
1 |
100.00 |
|
|
kmac_test_vectors_sha3_256 |
30.530s |
1.874ms |
1 |
1 |
100.00 |
|
|
kmac_test_vectors_sha3_384 |
18.738m |
52.976ms |
1 |
1 |
100.00 |
|
|
kmac_test_vectors_sha3_512 |
13.099m |
71.445ms |
1 |
1 |
100.00 |
|
|
kmac_test_vectors_shake_128 |
2.945m |
25.560ms |
1 |
1 |
100.00 |
|
|
kmac_test_vectors_shake_256 |
4.589m |
52.190ms |
1 |
1 |
100.00 |
|
|
kmac_test_vectors_kmac |
3.050s |
109.115us |
1 |
1 |
100.00 |
|
|
kmac_test_vectors_kmac_xof |
2.410s |
271.009us |
1 |
1 |
100.00 |
| V2 |
sideload |
kmac_sideload |
4.619m |
18.976ms |
1 |
1 |
100.00 |
| V2 |
app |
kmac_app |
4.054m |
15.092ms |
1 |
1 |
100.00 |
| V2 |
app_with_partial_data |
kmac_app_with_partial_data |
2.230m |
36.814ms |
1 |
1 |
100.00 |
| V2 |
entropy_refresh |
kmac_entropy_refresh |
2.568m |
37.866ms |
1 |
1 |
100.00 |
| V2 |
error |
kmac_error |
43.210s |
9.958ms |
1 |
1 |
100.00 |
| V2 |
key_error |
kmac_key_error |
8.030s |
919.544us |
1 |
1 |
100.00 |
| V2 |
sideload_invalid |
kmac_sideload_invalid |
3.940s |
114.856us |
1 |
1 |
100.00 |
| V2 |
edn_timeout_error |
kmac_edn_timeout_error |
29.890s |
1.998ms |
1 |
1 |
100.00 |
| V2 |
entropy_mode_error |
kmac_entropy_mode_error |
14.120s |
400.707us |
1 |
1 |
100.00 |
| V2 |
entropy_ready_error |
kmac_entropy_ready_error |
4.110s |
418.942us |
1 |
1 |
100.00 |
| V2 |
lc_escalation |
kmac_lc_escalation |
1.660s |
111.879us |
1 |
1 |
100.00 |
| V2 |
stress_all |
kmac_stress_all |
8.890m |
170.397ms |
1 |
1 |
100.00 |
| V2 |
intr_test |
kmac_intr_test |
0.860s |
16.981us |
1 |
1 |
100.00 |
| V2 |
alert_test |
kmac_alert_test |
1.070s |
143.224us |
1 |
1 |
100.00 |
| V2 |
tl_d_oob_addr_access |
kmac_tl_errors |
1.280s |
83.642us |
1 |
1 |
100.00 |
| V2 |
tl_d_illegal_access |
kmac_tl_errors |
1.280s |
83.642us |
1 |
1 |
100.00 |
| V2 |
tl_d_outstanding_access |
kmac_csr_hw_reset |
0.970s |
36.922us |
1 |
1 |
100.00 |
|
|
kmac_csr_rw |
1.200s |
29.532us |
1 |
1 |
100.00 |
|
|
kmac_csr_aliasing |
5.410s |
136.648us |
1 |
1 |
100.00 |
|
|
kmac_same_csr_outstanding |
2.410s |
90.138us |
1 |
1 |
100.00 |
| V2 |
tl_d_partial_access |
kmac_csr_hw_reset |
0.970s |
36.922us |
1 |
1 |
100.00 |
|
|
kmac_csr_rw |
1.200s |
29.532us |
1 |
1 |
100.00 |
|
|
kmac_csr_aliasing |
5.410s |
136.648us |
1 |
1 |
100.00 |
|
|
kmac_same_csr_outstanding |
2.410s |
90.138us |
1 |
1 |
100.00 |
| V2 |
|
TOTAL |
|
|
26 |
26 |
100.00 |
| V2S |
shadow_reg_update_error |
kmac_shadow_reg_errors |
1.620s |
59.417us |
1 |
1 |
100.00 |
| V2S |
shadow_reg_read_clear_staged_value |
kmac_shadow_reg_errors |
1.620s |
59.417us |
1 |
1 |
100.00 |
| V2S |
shadow_reg_storage_error |
kmac_shadow_reg_errors |
1.620s |
59.417us |
1 |
1 |
100.00 |
| V2S |
shadowed_reset_glitch |
kmac_shadow_reg_errors |
1.620s |
59.417us |
1 |
1 |
100.00 |
| V2S |
shadow_reg_update_error_with_csr_rw |
kmac_shadow_reg_errors_with_csr_rw |
4.040s |
492.543us |
1 |
1 |
100.00 |
| V2S |
tl_intg_err |
kmac_sec_cm |
1.036m |
13.299ms |
1 |
1 |
100.00 |
|
|
kmac_tl_intg_err |
3.530s |
291.663us |
1 |
1 |
100.00 |
| V2S |
sec_cm_bus_integrity |
kmac_tl_intg_err |
3.530s |
291.663us |
1 |
1 |
100.00 |
| V2S |
sec_cm_lc_escalate_en_intersig_mubi |
kmac_lc_escalation |
1.660s |
111.879us |
1 |
1 |
100.00 |
| V2S |
sec_cm_sw_key_key_masking |
kmac_smoke |
10.040s |
622.035us |
1 |
1 |
100.00 |
| V2S |
sec_cm_key_sideload |
kmac_sideload |
4.619m |
18.976ms |
1 |
1 |
100.00 |
| V2S |
sec_cm_cfg_shadowed_config_shadow |
kmac_shadow_reg_errors |
1.620s |
59.417us |
1 |
1 |
100.00 |
| V2S |
sec_cm_fsm_sparse |
kmac_sec_cm |
1.036m |
13.299ms |
1 |
1 |
100.00 |
| V2S |
sec_cm_ctr_redun |
kmac_sec_cm |
1.036m |
13.299ms |
1 |
1 |
100.00 |
| V2S |
sec_cm_packer_ctr_redun |
kmac_sec_cm |
1.036m |
13.299ms |
1 |
1 |
100.00 |
| V2S |
sec_cm_cfg_shadowed_config_regwen |
kmac_smoke |
10.040s |
622.035us |
1 |
1 |
100.00 |
| V2S |
sec_cm_fsm_global_esc |
kmac_lc_escalation |
1.660s |
111.879us |
1 |
1 |
100.00 |
| V2S |
sec_cm_fsm_local_esc |
kmac_sec_cm |
1.036m |
13.299ms |
1 |
1 |
100.00 |
| V2S |
sec_cm_absorbed_ctrl_mubi |
kmac_mubi |
29.690s |
1.731ms |
1 |
1 |
100.00 |
| V2S |
sec_cm_sw_cmd_ctrl_sparse |
kmac_smoke |
10.040s |
622.035us |
1 |
1 |
100.00 |
| V2S |
|
TOTAL |
|
|
5 |
5 |
100.00 |
| V3 |
stress_all_with_rand_reset |
kmac_stress_all_with_rand_reset |
38.170s |
2.158ms |
1 |
1 |
100.00 |
| V3 |
|
TOTAL |
|
|
1 |
1 |
100.00 |
|
|
TOTAL |
|
|
40 |
40 |
100.00 |