OTBN Simulation Results

Tuesday October 07 2025 19:21:11 UTC

GitHub Revision: 25151e0

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke otbn_smoke 11.000s 116.105us 0 1 0.00
V1 single_binary otbn_single 16.000s 53.253us 0 1 0.00
V1 csr_hw_reset otbn_csr_hw_reset 8.000s 49.486us 1 1 100.00
V1 csr_rw otbn_csr_rw 4.000s 14.040us 1 1 100.00
V1 csr_bit_bash otbn_csr_bit_bash 5.000s 24.311us 1 1 100.00
V1 csr_aliasing otbn_csr_aliasing 4.000s 37.580us 1 1 100.00
V1 csr_mem_rw_with_rand_reset otbn_csr_mem_rw_with_rand_reset 4.000s 47.571us 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr otbn_csr_rw 4.000s 14.040us 1 1 100.00
otbn_csr_aliasing 4.000s 37.580us 1 1 100.00
V1 mem_walk otbn_mem_walk 19.000s 3.537ms 1 1 100.00
V1 mem_partial_access otbn_mem_partial_access 10.000s 207.913us 1 1 100.00
V1 TOTAL 7 9 77.78
V2 reset_recovery otbn_reset 20.000s 80.524us 0 1 0.00
V2 multi_error otbn_multi_err 42.000s 336.453us 0 1 0.00
V2 back_to_back otbn_multi 59.000s 653.773us 0 1 0.00
V2 stress_all otbn_stress_all 41.000s 356.054us 0 1 0.00
V2 lc_escalation otbn_escalate 8.000s 55.662us 0 1 0.00
V2 zero_state_err_urnd otbn_zero_state_err_urnd 5.000s 18.143us 1 1 100.00
V2 sw_errs_fatal_chk otbn_sw_errs_fatal_chk 30.000s 279.516us 0 1 0.00
V2 alert_test otbn_alert_test 3.000s 13.032us 1 1 100.00
V2 intr_test otbn_intr_test 4.000s 16.700us 1 1 100.00
V2 tl_d_oob_addr_access otbn_tl_errors 9.000s 59.666us 1 1 100.00
V2 tl_d_illegal_access otbn_tl_errors 9.000s 59.666us 1 1 100.00
V2 tl_d_outstanding_access otbn_csr_hw_reset 8.000s 49.486us 1 1 100.00
otbn_csr_rw 4.000s 14.040us 1 1 100.00
otbn_csr_aliasing 4.000s 37.580us 1 1 100.00
otbn_same_csr_outstanding 4.000s 143.786us 1 1 100.00
V2 tl_d_partial_access otbn_csr_hw_reset 8.000s 49.486us 1 1 100.00
otbn_csr_rw 4.000s 14.040us 1 1 100.00
otbn_csr_aliasing 4.000s 37.580us 1 1 100.00
otbn_same_csr_outstanding 4.000s 143.786us 1 1 100.00
V2 TOTAL 5 11 45.45
V2S mem_integrity otbn_imem_err 5.000s 12.354us 1 1 100.00
otbn_dmem_err 6.000s 16.730us 0 1 0.00
V2S internal_integrity otbn_alu_bignum_mod_err 7.000s 207.634us 0 1 0.00
otbn_controller_ispr_rdata_err 7.000s 90.412us 0 1 0.00
otbn_mac_bignum_acc_err 8.000s 116.863us 0 1 0.00
otbn_urnd_err 4.000s 40.094us 1 1 100.00
V2S illegal_bus_access otbn_illegal_mem_acc 4.000s 14.336us 1 1 100.00
V2S otbn_mem_gnt_acc_err otbn_mem_gnt_acc_err 5.000s 29.021us 1 1 100.00
V2S otbn_non_sec_partial_wipe otbn_partial_wipe 5.000s 128.500us 0 1 0.00
V2S tl_intg_err otbn_sec_cm 3.233m 1.206ms 1 1 100.00
otbn_tl_intg_err 9.000s 395.730us 1 1 100.00
V2S passthru_mem_tl_intg_err otbn_passthru_mem_tl_intg_err 12.000s 105.072us 1 1 100.00
V2S prim_fsm_check otbn_sec_cm 3.233m 1.206ms 1 1 100.00
V2S prim_count_check otbn_sec_cm 3.233m 1.206ms 1 1 100.00
V2S sec_cm_mem_scramble otbn_smoke 11.000s 116.105us 0 1 0.00
V2S sec_cm_data_mem_integrity otbn_dmem_err 6.000s 16.730us 0 1 0.00
V2S sec_cm_instruction_mem_integrity otbn_imem_err 5.000s 12.354us 1 1 100.00
V2S sec_cm_bus_integrity otbn_tl_intg_err 9.000s 395.730us 1 1 100.00
V2S sec_cm_controller_fsm_global_esc otbn_escalate 8.000s 55.662us 0 1 0.00
V2S sec_cm_controller_fsm_local_esc otbn_imem_err 5.000s 12.354us 1 1 100.00
otbn_dmem_err 6.000s 16.730us 0 1 0.00
otbn_zero_state_err_urnd 5.000s 18.143us 1 1 100.00
otbn_illegal_mem_acc 4.000s 14.336us 1 1 100.00
otbn_sec_cm 3.233m 1.206ms 1 1 100.00
V2S sec_cm_controller_fsm_sparse otbn_sec_cm 3.233m 1.206ms 1 1 100.00
V2S sec_cm_scramble_key_sideload otbn_single 16.000s 53.253us 0 1 0.00
V2S sec_cm_scramble_ctrl_fsm_local_esc otbn_imem_err 5.000s 12.354us 1 1 100.00
otbn_dmem_err 6.000s 16.730us 0 1 0.00
otbn_zero_state_err_urnd 5.000s 18.143us 1 1 100.00
otbn_illegal_mem_acc 4.000s 14.336us 1 1 100.00
otbn_sec_cm 3.233m 1.206ms 1 1 100.00
V2S sec_cm_scramble_ctrl_fsm_sparse otbn_sec_cm 3.233m 1.206ms 1 1 100.00
V2S sec_cm_start_stop_ctrl_fsm_global_esc otbn_escalate 8.000s 55.662us 0 1 0.00
V2S sec_cm_start_stop_ctrl_fsm_local_esc otbn_imem_err 5.000s 12.354us 1 1 100.00
otbn_dmem_err 6.000s 16.730us 0 1 0.00
otbn_zero_state_err_urnd 5.000s 18.143us 1 1 100.00
otbn_illegal_mem_acc 4.000s 14.336us 1 1 100.00
otbn_sec_cm 3.233m 1.206ms 1 1 100.00
V2S sec_cm_start_stop_ctrl_fsm_sparse otbn_sec_cm 3.233m 1.206ms 1 1 100.00
V2S sec_cm_data_reg_sw_sca otbn_single 16.000s 53.253us 0 1 0.00
V2S sec_cm_ctrl_redun otbn_ctrl_redun 5.000s 51.855us 0 1 0.00
V2S sec_cm_pc_ctrl_flow_redun otbn_pc_ctrl_flow_redun 6.000s 20.718us 1 1 100.00
V2S sec_cm_rnd_bus_consistency otbn_rnd_sec_cm 1.050m 1.353ms 0 1 0.00
V2S sec_cm_rnd_rng_digest otbn_rnd_sec_cm 1.050m 1.353ms 0 1 0.00
V2S sec_cm_rf_base_data_reg_sw_integrity otbn_rf_base_intg_err 6.000s 70.986us 0 1 0.00
V2S sec_cm_rf_base_data_reg_sw_glitch_detect otbn_sec_cm 3.233m 1.206ms 1 1 100.00
V2S sec_cm_stack_wr_ptr_ctr_redun otbn_sec_cm 3.233m 1.206ms 1 1 100.00
V2S sec_cm_rf_bignum_data_reg_sw_integrity otbn_rf_bignum_intg_err 13.000s 91.020us 0 1 0.00
V2S sec_cm_rf_bignum_data_reg_sw_glitch_detect otbn_sec_cm 3.233m 1.206ms 1 1 100.00
V2S sec_cm_loop_stack_ctr_redun otbn_sec_cm 3.233m 1.206ms 1 1 100.00
V2S sec_cm_loop_stack_addr_integrity otbn_stack_addr_integ_chk 13.000s 46.534us 0 1 0.00
V2S sec_cm_call_stack_addr_integrity otbn_stack_addr_integ_chk 13.000s 46.534us 0 1 0.00
V2S sec_cm_start_stop_ctrl_state_consistency otbn_sec_wipe_err 4.000s 15.077us 1 1 100.00
V2S sec_cm_data_mem_sec_wipe otbn_single 16.000s 53.253us 0 1 0.00
V2S sec_cm_instruction_mem_sec_wipe otbn_single 16.000s 53.253us 0 1 0.00
V2S sec_cm_data_reg_sw_sec_wipe otbn_single 16.000s 53.253us 0 1 0.00
V2S sec_cm_write_mem_integrity otbn_multi 59.000s 653.773us 0 1 0.00
V2S sec_cm_ctrl_flow_count otbn_single 16.000s 53.253us 0 1 0.00
V2S sec_cm_ctrl_flow_sca otbn_single 16.000s 53.253us 0 1 0.00
V2S sec_cm_data_mem_sw_noaccess otbn_sw_no_acc 5.000s 35.426us 0 1 0.00
V2S sec_cm_key_sideload otbn_single 16.000s 53.253us 0 1 0.00
V2S sec_cm_tlul_fifo_ctr_redun otbn_sec_cm 3.233m 1.206ms 1 1 100.00
V2S TOTAL 9 20 45.00
V3 stress_all_with_rand_reset otbn_stress_all_with_rand_reset 37.000s 1.125ms 0 1 0.00
V3 TOTAL 0 1 0.00
TOTAL 21 41 51.22

Failure Buckets