ROM_CTRL/32KB Simulation Results

Tuesday October 07 2025 19:21:11 UTC

GitHub Revision: 25151e0

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	rom_ctrl_smoke	4.360s	142.813us	1	1	100.00
V1	csr_hw_reset	rom_ctrl_csr_hw_reset	6.290s	554.550us	1	1	100.00
V1	csr_rw	rom_ctrl_csr_rw	3.480s	212.030us	1	1	100.00
V1	csr_bit_bash	rom_ctrl_csr_bit_bash	4.420s	435.203us	1	1	100.00
V1	csr_aliasing	rom_ctrl_csr_aliasing	4.260s	792.685us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	rom_ctrl_csr_mem_rw_with_rand_reset	4.770s	319.097us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rom_ctrl_csr_rw	3.480s	212.030us	1	1	100.00
		rom_ctrl_csr_aliasing	4.260s	792.685us	1	1	100.00
V1	mem_walk	rom_ctrl_mem_walk	3.690s	538.693us	1	1	100.00
V1	mem_partial_access	rom_ctrl_mem_partial_access	4.100s	265.257us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	max_throughput_chk	rom_ctrl_max_throughput_chk	3.980s	224.952us	1	1	100.00
V2	stress_all	rom_ctrl_stress_all	15.300s	5.696ms	1	1	100.00
V2	kmac_err_chk	rom_ctrl_kmac_err_chk	8.260s	300.199us	1	1	100.00
V2	alert_test	rom_ctrl_alert_test	3.420s	209.479us	1	1	100.00
V2	tl_d_oob_addr_access	rom_ctrl_tl_errors	5.230s	128.657us	1	1	100.00
V2	tl_d_illegal_access	rom_ctrl_tl_errors	5.230s	128.657us	1	1	100.00
V2	tl_d_outstanding_access	rom_ctrl_csr_hw_reset	6.290s	554.550us	1	1	100.00
		rom_ctrl_csr_rw	3.480s	212.030us	1	1	100.00
		rom_ctrl_csr_aliasing	4.260s	792.685us	1	1	100.00
		rom_ctrl_same_csr_outstanding	3.810s	991.568us	1	1	100.00
V2	tl_d_partial_access	rom_ctrl_csr_hw_reset	6.290s	554.550us	1	1	100.00
		rom_ctrl_csr_rw	3.480s	212.030us	1	1	100.00
		rom_ctrl_csr_aliasing	4.260s	792.685us	1	1	100.00
		rom_ctrl_same_csr_outstanding	3.810s	991.568us	1	1	100.00
V2		TOTAL			6	6	100.00
V2S	corrupt_sig_fatal_chk	rom_ctrl_corrupt_sig_fatal_chk	22.240s	295.506us	0	1	0.00
V2S	passthru_mem_tl_intg_err	rom_ctrl_passthru_mem_tl_intg_err	20.380s	3.182ms	1	1	100.00
V2S	tl_intg_err	rom_ctrl_sec_cm	3.345m	711.660us	0	1	0.00
		rom_ctrl_tl_intg_err	27.880s	290.984us	1	1	100.00
V2S	prim_fsm_check	rom_ctrl_sec_cm	3.345m	711.660us	0	1	0.00
V2S	prim_count_check	rom_ctrl_sec_cm	3.345m	711.660us	0	1	0.00
V2S	sec_cm_checker_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	22.240s	295.506us	0	1	0.00
V2S	sec_cm_checker_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	22.240s	295.506us	0	1	0.00
V2S	sec_cm_checker_fsm_local_esc	rom_ctrl_corrupt_sig_fatal_chk	22.240s	295.506us	0	1	0.00
V2S	sec_cm_compare_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	22.240s	295.506us	0	1	0.00
V2S	sec_cm_compare_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	22.240s	295.506us	0	1	0.00
V2S	sec_cm_compare_ctr_redun	rom_ctrl_sec_cm	3.345m	711.660us	0	1	0.00
V2S	sec_cm_fsm_sparse	rom_ctrl_sec_cm	3.345m	711.660us	0	1	0.00
V2S	sec_cm_mem_scramble	rom_ctrl_smoke	4.360s	142.813us	1	1	100.00
V2S	sec_cm_mem_digest	rom_ctrl_smoke	4.360s	142.813us	1	1	100.00
V2S	sec_cm_intersig_mubi	rom_ctrl_smoke	4.360s	142.813us	1	1	100.00
V2S	sec_cm_bus_integrity	rom_ctrl_tl_intg_err	27.880s	290.984us	1	1	100.00
V2S	sec_cm_bus_local_esc	rom_ctrl_corrupt_sig_fatal_chk	22.240s	295.506us	0	1	0.00
		rom_ctrl_kmac_err_chk	8.260s	300.199us	1	1	100.00
V2S	sec_cm_mux_mubi	rom_ctrl_corrupt_sig_fatal_chk	22.240s	295.506us	0	1	0.00
V2S	sec_cm_mux_consistency	rom_ctrl_corrupt_sig_fatal_chk	22.240s	295.506us	0	1	0.00
V2S	sec_cm_ctrl_redun	rom_ctrl_corrupt_sig_fatal_chk	22.240s	295.506us	0	1	0.00
V2S	sec_cm_ctrl_mem_integrity	rom_ctrl_passthru_mem_tl_intg_err	20.380s	3.182ms	1	1	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	rom_ctrl_sec_cm	3.345m	711.660us	0	1	0.00
V2S		TOTAL			2	4	50.00
V3	stress_all_with_rand_reset	rom_ctrl_stress_all_with_rand_reset	4.967m	3.983ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			17	19	89.47

Failure Buckets

• UVM_ERROR (rom_ctrl_corrupt_sig_fatal_chk_vseq.sv:149) [rom_ctrl_corrupt_sig_fatal_chk_vseq] Check failed (cfg.rom_ctrl_vif.pwrmgr_data.done != MuBi4True) has 1 failures:

  • Test rom_ctrl_corrupt_sig_fatal_chk has 1 failures.

    • 0.rom_ctrl_corrupt_sig_fatal_chk.71309004614831151592600537521793442486033130574522409532962475304299435746782
      Line 94, in log /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-vcs/0.rom_ctrl_corrupt_sig_fatal_chk/latest/run.log

        UVM_ERROR @ 295506245 ps: (rom_ctrl_corrupt_sig_fatal_chk_vseq.sv:149) [uvm_test_top.env.virtual_sequencer.rom_ctrl_corrupt_sig_fatal_chk_vseq] Check failed (cfg.rom_ctrl_vif.pwrmgr_data.done != MuBi4True)
        UVM_INFO @ 295506245 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• Offending '(d2h.d_opcode === (((curr_fwd ? curr_req.opcode : pend_req[d2h.d_source].opcode) == Get) ? AccessAckData : AccessAck))' has 1 failures:

  • Test rom_ctrl_sec_cm has 1 failures.

    • 0.rom_ctrl_sec_cm.36914557758643993654691690095317115152353325884375296885199106275483135244114
      Line 243, in log /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-vcs/0.rom_ctrl_sec_cm/latest/run.log

            Offending '(d2h.d_opcode === (((curr_fwd ? curr_req.opcode : pend_req[d2h.d_source].opcode) == Get) ? AccessAckData : AccessAck))'
        "src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 292: tb.dut.rom_tlul_assert_device.gen_device.gen_d2h.respSzEqReqSz_A: started at 22109736ps failed at 22109736ps
            Offending '(d2h.d_size === (curr_fwd ? curr_req.size : pend_req[d2h.d_source].size))'
        "src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 293: tb.dut.rom_tlul_assert_device.gen_device.gen_d2h.respMustHaveReq_A: started at 22109736ps failed at 22109736ps
            Offending '(curr_fwd | pend_req[d2h.d_source].pend)'