25151e0| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | random | rv_timer_random | 1.240s | 640.700us | 1 | 1 | 100.00 |
| V1 | csr_hw_reset | rv_timer_csr_hw_reset | 0.610s | 22.443us | 1 | 1 | 100.00 |
| V1 | csr_rw | rv_timer_csr_rw | 0.680s | 118.189us | 1 | 1 | 100.00 |
| V1 | csr_bit_bash | rv_timer_csr_bit_bash | 1.760s | 412.130us | 1 | 1 | 100.00 |
| V1 | csr_aliasing | rv_timer_csr_aliasing | 0.770s | 90.782us | 1 | 1 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | rv_timer_csr_mem_rw_with_rand_reset | 0.950s | 64.263us | 1 | 1 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | rv_timer_csr_rw | 0.680s | 118.189us | 1 | 1 | 100.00 |
| rv_timer_csr_aliasing | 0.770s | 90.782us | 1 | 1 | 100.00 | ||
| V1 | TOTAL | 6 | 6 | 100.00 | |||
| V2 | random_reset | rv_timer_random_reset | 0.800s | 652.537us | 0 | 1 | 0.00 |
| V2 | disabled | rv_timer_disabled | 0.840s | 1.123ms | 1 | 1 | 100.00 |
| V2 | cfg_update_on_fly | rv_timer_cfg_update_on_fly | 2.056m | 333.288ms | 1 | 1 | 100.00 |
| V2 | no_interrupt_test | rv_timer_cfg_update_on_fly | 2.056m | 333.288ms | 1 | 1 | 100.00 |
| V2 | stress | rv_timer_stress_all | 3.980s | 3.227ms | 1 | 1 | 100.00 |
| V2 | alert_test | rv_timer_alert_test | 0.530s | 107.108us | 1 | 1 | 100.00 |
| V2 | intr_test | rv_timer_intr_test | 0.760s | 13.551us | 1 | 1 | 100.00 |
| V2 | tl_d_oob_addr_access | rv_timer_tl_errors | 1.630s | 140.709us | 1 | 1 | 100.00 |
| V2 | tl_d_illegal_access | rv_timer_tl_errors | 1.630s | 140.709us | 1 | 1 | 100.00 |
| V2 | tl_d_outstanding_access | rv_timer_csr_hw_reset | 0.610s | 22.443us | 1 | 1 | 100.00 |
| rv_timer_csr_rw | 0.680s | 118.189us | 1 | 1 | 100.00 | ||
| rv_timer_csr_aliasing | 0.770s | 90.782us | 1 | 1 | 100.00 | ||
| rv_timer_same_csr_outstanding | 0.720s | 24.573us | 1 | 1 | 100.00 | ||
| V2 | tl_d_partial_access | rv_timer_csr_hw_reset | 0.610s | 22.443us | 1 | 1 | 100.00 |
| rv_timer_csr_rw | 0.680s | 118.189us | 1 | 1 | 100.00 | ||
| rv_timer_csr_aliasing | 0.770s | 90.782us | 1 | 1 | 100.00 | ||
| rv_timer_same_csr_outstanding | 0.720s | 24.573us | 1 | 1 | 100.00 | ||
| V2 | TOTAL | 7 | 8 | 87.50 | |||
| V2S | tl_intg_err | rv_timer_sec_cm | 0.800s | 1.020ms | 1 | 1 | 100.00 |
| rv_timer_tl_intg_err | 1.350s | 135.447us | 1 | 1 | 100.00 | ||
| V2S | sec_cm_bus_integrity | rv_timer_tl_intg_err | 1.350s | 135.447us | 1 | 1 | 100.00 |
| V2S | TOTAL | 2 | 2 | 100.00 | |||
| V3 | min_value | rv_timer_min | 0.780s | 140.800us | 0 | 1 | 0.00 |
| V3 | max_value | rv_timer_max | 1.470s | 182.255us | 0 | 1 | 0.00 |
| V3 | stress_all_with_rand_reset | rv_timer_stress_all_with_rand_reset | 10.020s | 7.759ms | 1 | 1 | 100.00 |
| V3 | TOTAL | 1 | 3 | 33.33 | |||
| TOTAL | 16 | 19 | 84.21 |
UVM_FATAL (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state* (addr=*) == * has 2 failures:
Test rv_timer_min has 1 failures.
0.rv_timer_min.17738953105763140702180771171450028321771585980954948793440403333389174274035
Line 72, in log /nightly/current_run/scratch/master/rv_timer-sim-vcs/0.rv_timer_min/latest/run.log
UVM_FATAL @ 140800069 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0x73e7d504) == 0x1
UVM_INFO @ 140800069 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test rv_timer_random_reset has 1 failures.
0.rv_timer_random_reset.33602858503203249785112916216079489908045878392261216434772615518986830742669
Line 73, in log /nightly/current_run/scratch/master/rv_timer-sim-vcs/0.rv_timer_random_reset/latest/run.log
UVM_FATAL @ 652536557 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0x8b081104) == 0x1
UVM_INFO @ 652536557 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_timer_scoreboard.sv:250) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) has 1 failures:
0.rv_timer_max.4243022219356794322651699872993604495340281532013859866414581525026601756799
Line 72, in log /nightly/current_run/scratch/master/rv_timer-sim-vcs/0.rv_timer_max/latest/run.log
UVM_ERROR @ 182254938 ps: (rv_timer_scoreboard.sv:250) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0])
UVM_INFO @ 182254938 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---