SPI_DEVICE/1R1W Simulation Results

Tuesday October 07 2025 19:21:11 UTC

GitHub Revision: 25151e0

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_device_flash_and_tpm	50.050s	13.823ms	1	1	100.00
V1	csr_hw_reset	spi_device_csr_hw_reset	0.980s	22.749us	1	1	100.00
V1	csr_rw	spi_device_csr_rw	1.460s	48.763us	1	1	100.00
V1	csr_bit_bash	spi_device_csr_bit_bash	24.110s	537.238us	1	1	100.00
V1	csr_aliasing	spi_device_csr_aliasing	14.780s	1.194ms	1	1	100.00
V1	csr_mem_rw_with_rand_reset	spi_device_csr_mem_rw_with_rand_reset	2.720s	55.528us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_device_csr_rw	1.460s	48.763us	1	1	100.00
		spi_device_csr_aliasing	14.780s	1.194ms	1	1	100.00
V1	mem_walk	spi_device_mem_walk	0.800s	31.963us	1	1	100.00
V1	mem_partial_access	spi_device_mem_partial_access	1.160s	38.152us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	csb_read	spi_device_csb_read	0.970s	33.081us	1	1	100.00
V2	mem_parity	spi_device_mem_parity	0.670s	3.417us	0	1	0.00
V2	mem_cfg	spi_device_ram_cfg	0.720s	4.143us	0	1	0.00
V2	tpm_read	spi_device_tpm_rw	3.820s	4.889ms	1	1	100.00
V2	tpm_write	spi_device_tpm_rw	3.820s	4.889ms	1	1	100.00
V2	tpm_hw_reg	spi_device_tpm_read_hw_reg	0.840s	22.123us	1	1	100.00
		spi_device_tpm_sts_read	0.960s	56.068us	1	1	100.00
V2	tpm_fully_random_case	spi_device_tpm_all	15.000s	5.189ms	1	1	100.00
V2	pass_cmd_filtering	spi_device_pass_cmd_filtering	2.740s	238.794us	1	1	100.00
		spi_device_flash_all	2.633m	234.457ms	1	1	100.00
V2	pass_addr_translation	spi_device_pass_addr_payload_swap	1.990s	37.859us	1	1	100.00
		spi_device_flash_all	2.633m	234.457ms	1	1	100.00
V2	pass_payload_translation	spi_device_pass_addr_payload_swap	1.990s	37.859us	1	1	100.00
		spi_device_flash_all	2.633m	234.457ms	1	1	100.00
V2	cmd_info_slots	spi_device_flash_all	2.633m	234.457ms	1	1	100.00
V2	cmd_read_status	spi_device_intercept	8.300s	5.058ms	1	1	100.00
		spi_device_flash_all	2.633m	234.457ms	1	1	100.00
V2	cmd_read_jedec	spi_device_intercept	8.300s	5.058ms	1	1	100.00
		spi_device_flash_all	2.633m	234.457ms	1	1	100.00
V2	cmd_read_sfdp	spi_device_intercept	8.300s	5.058ms	1	1	100.00
		spi_device_flash_all	2.633m	234.457ms	1	1	100.00
V2	cmd_fast_read	spi_device_intercept	8.300s	5.058ms	1	1	100.00
		spi_device_flash_all	2.633m	234.457ms	1	1	100.00
V2	cmd_read_pipeline	spi_device_intercept	8.300s	5.058ms	1	1	100.00
		spi_device_flash_all	2.633m	234.457ms	1	1	100.00
V2	flash_cmd_upload	spi_device_upload	5.740s	3.507ms	1	1	100.00
V2	mailbox_command	spi_device_mailbox	22.750s	36.602ms	1	1	100.00
V2	mailbox_cross_outside_command	spi_device_mailbox	22.750s	36.602ms	1	1	100.00
V2	mailbox_cross_inside_command	spi_device_mailbox	22.750s	36.602ms	1	1	100.00
V2	cmd_read_buffer	spi_device_flash_mode	9.600s	619.529us	1	1	100.00
		spi_device_read_buffer_direct	3.870s	301.739us	1	1	100.00
V2	cmd_dummy_cycle	spi_device_mailbox	22.750s	36.602ms	1	1	100.00
		spi_device_flash_all	2.633m	234.457ms	1	1	100.00
V2	quad_spi	spi_device_flash_all	2.633m	234.457ms	1	1	100.00
V2	dual_spi	spi_device_flash_all	2.633m	234.457ms	1	1	100.00
V2	4b_3b_feature	spi_device_cfg_cmd	3.600s	587.068us	1	1	100.00
V2	write_enable_disable	spi_device_cfg_cmd	3.600s	587.068us	1	1	100.00
V2	TPM_with_flash_or_passthrough_mode	spi_device_flash_and_tpm	50.050s	13.823ms	1	1	100.00
V2	tpm_and_flash_trans_with_min_inactive_time	spi_device_flash_and_tpm_min_idle	1.486m	41.199ms	1	1	100.00
V2	stress_all	spi_device_stress_all	52.100s	9.074ms	1	1	100.00
V2	alert_test	spi_device_alert_test	1.040s	12.314us	1	1	100.00
V2	intr_test	spi_device_intr_test	1.010s	46.298us	1	1	100.00
V2	tl_d_oob_addr_access	spi_device_tl_errors	3.010s	227.401us	1	1	100.00
V2	tl_d_illegal_access	spi_device_tl_errors	3.010s	227.401us	1	1	100.00
V2	tl_d_outstanding_access	spi_device_csr_hw_reset	0.980s	22.749us	1	1	100.00
		spi_device_csr_rw	1.460s	48.763us	1	1	100.00
		spi_device_csr_aliasing	14.780s	1.194ms	1	1	100.00
		spi_device_same_csr_outstanding	2.540s	521.402us	1	1	100.00
V2	tl_d_partial_access	spi_device_csr_hw_reset	0.980s	22.749us	1	1	100.00
		spi_device_csr_rw	1.460s	48.763us	1	1	100.00
		spi_device_csr_aliasing	14.780s	1.194ms	1	1	100.00
		spi_device_same_csr_outstanding	2.540s	521.402us	1	1	100.00
V2		TOTAL			20	22	90.91
V2S	tl_intg_err	spi_device_sec_cm	1.270s	259.486us	1	1	100.00
		spi_device_tl_intg_err	11.540s	1.168ms	1	1	100.00
V2S	sec_cm_bus_integrity	spi_device_tl_intg_err	11.540s	1.168ms	1	1	100.00
V2S		TOTAL			2	2	100.00
	Unmapped tests	spi_device_flash_mode_ignore_cmds	50.550s	20.619ms	1	1	100.00
		TOTAL			31	33	93.94

Failure Buckets

• UVM_ERROR (uvm_hdl_vcs.c:1035) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[*]) has 1 failures:

  • Test spi_device_mem_parity has 1 failures.

    • 0.spi_device_mem_parity.74777548182584749708095337359708243460280699172797612868883428902171724905752
      Line 73, in log /nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/0.spi_device_mem_parity/latest/run.log

        UVM_ERROR @   2654304 ps: (uvm_hdl_vcs.c:1035) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[35])
         Either the name is incorrect, or you may not have PLI/ACC visibility to that name
        UVM_ERROR @   2654304 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
        UVM_ERROR @   2654304 ps: (uvm_hdl_vcs.c:1185) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[931])
         Either the name is incorrect, or you may not have PLI/ACC visibility to that name
      

• UVM_ERROR (spi_device_ram_cfg_vseq.sv:27) [spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (* [*] vs * [*]) has 1 failures:

  • Test spi_device_ram_cfg has 1 failures.

    • 0.spi_device_ram_cfg.61127678243059030362916366320029663923535711449522690583682420749255944839704
      Line 73, in log /nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/0.spi_device_ram_cfg/latest/run.log

        UVM_ERROR @   1676646 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xaba7ef [101010111010011111101111] vs 0x0 [0])
        UVM_ERROR @   1708646 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xe14cda [111000010100110011011010] vs 0x0 [0])
        UVM_ERROR @   1762646 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xf0e809 [111100001110100000001001] vs 0x0 [0])
        UVM_ERROR @   1779646 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x9a50fd [100110100101000011111101] vs 0x0 [0])
        UVM_ERROR @   1798646 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xcd7e50 [110011010111111001010000] vs 0x0 [0])