SPI_DEVICE/2P Simulation Results

Tuesday October 07 2025 19:21:11 UTC

GitHub Revision: 25151e0

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_device_flash_and_tpm	44.600s	9.232ms	1	1	100.00
V1	csr_hw_reset	spi_device_csr_hw_reset	0.830s	44.048us	1	1	100.00
V1	csr_rw	spi_device_csr_rw	1.360s	104.920us	1	1	100.00
V1	csr_bit_bash	spi_device_csr_bit_bash	29.070s	5.539ms	1	1	100.00
V1	csr_aliasing	spi_device_csr_aliasing	11.450s	3.732ms	1	1	100.00
V1	csr_mem_rw_with_rand_reset	spi_device_csr_mem_rw_with_rand_reset	1.390s	33.943us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_device_csr_rw	1.360s	104.920us	1	1	100.00
		spi_device_csr_aliasing	11.450s	3.732ms	1	1	100.00
V1	mem_walk	spi_device_mem_walk	0.640s	43.503us	1	1	100.00
V1	mem_partial_access	spi_device_mem_partial_access	1.090s	20.312us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	csb_read	spi_device_csb_read	0.770s	14.141us	1	1	100.00
V2	mem_parity	spi_device_mem_parity	0.900s	60.790us	1	1	100.00
V2	mem_cfg	spi_device_ram_cfg	0.680s	26.792us	1	1	100.00
V2	tpm_read	spi_device_tpm_rw	0.670s	29.818us	1	1	100.00
V2	tpm_write	spi_device_tpm_rw	0.670s	29.818us	1	1	100.00
V2	tpm_hw_reg	spi_device_tpm_read_hw_reg	2.710s	2.317ms	1	1	100.00
		spi_device_tpm_sts_read	0.690s	38.086us	1	1	100.00
V2	tpm_fully_random_case	spi_device_tpm_all	14.620s	3.477ms	1	1	100.00
V2	pass_cmd_filtering	spi_device_pass_cmd_filtering	4.190s	2.988ms	1	1	100.00
		spi_device_flash_all	16.420s	1.834ms	1	1	100.00
V2	pass_addr_translation	spi_device_pass_addr_payload_swap	3.880s	1.276ms	1	1	100.00
		spi_device_flash_all	16.420s	1.834ms	1	1	100.00
V2	pass_payload_translation	spi_device_pass_addr_payload_swap	3.880s	1.276ms	1	1	100.00
		spi_device_flash_all	16.420s	1.834ms	1	1	100.00
V2	cmd_info_slots	spi_device_flash_all	16.420s	1.834ms	1	1	100.00
V2	cmd_read_status	spi_device_intercept	21.000s	14.091ms	1	1	100.00
		spi_device_flash_all	16.420s	1.834ms	1	1	100.00
V2	cmd_read_jedec	spi_device_intercept	21.000s	14.091ms	1	1	100.00
		spi_device_flash_all	16.420s	1.834ms	1	1	100.00
V2	cmd_read_sfdp	spi_device_intercept	21.000s	14.091ms	1	1	100.00
		spi_device_flash_all	16.420s	1.834ms	1	1	100.00
V2	cmd_fast_read	spi_device_intercept	21.000s	14.091ms	1	1	100.00
		spi_device_flash_all	16.420s	1.834ms	1	1	100.00
V2	cmd_read_pipeline	spi_device_intercept	21.000s	14.091ms	1	1	100.00
		spi_device_flash_all	16.420s	1.834ms	1	1	100.00
V2	flash_cmd_upload	spi_device_upload	9.780s	25.580ms	1	1	100.00
V2	mailbox_command	spi_device_mailbox	45.060s	8.524ms	1	1	100.00
V2	mailbox_cross_outside_command	spi_device_mailbox	45.060s	8.524ms	1	1	100.00
V2	mailbox_cross_inside_command	spi_device_mailbox	45.060s	8.524ms	1	1	100.00
V2	cmd_read_buffer	spi_device_flash_mode	3.660s	274.427us	1	1	100.00
		spi_device_read_buffer_direct	3.660s	1.113ms	1	1	100.00
V2	cmd_dummy_cycle	spi_device_mailbox	45.060s	8.524ms	1	1	100.00
		spi_device_flash_all	16.420s	1.834ms	1	1	100.00
V2	quad_spi	spi_device_flash_all	16.420s	1.834ms	1	1	100.00
V2	dual_spi	spi_device_flash_all	16.420s	1.834ms	1	1	100.00
V2	4b_3b_feature	spi_device_cfg_cmd	2.760s	694.578us	1	1	100.00
V2	write_enable_disable	spi_device_cfg_cmd	2.760s	694.578us	1	1	100.00
V2	TPM_with_flash_or_passthrough_mode	spi_device_flash_and_tpm	44.600s	9.232ms	1	1	100.00
V2	tpm_and_flash_trans_with_min_inactive_time	spi_device_flash_and_tpm_min_idle	2.119m	122.224ms	1	1	100.00
V2	stress_all	spi_device_stress_all	7.500s	3.776ms	1	1	100.00
V2	alert_test	spi_device_alert_test	0.820s	25.639us	1	1	100.00
V2	intr_test	spi_device_intr_test	0.700s	140.801us	1	1	100.00
V2	tl_d_oob_addr_access	spi_device_tl_errors	4.080s	1.062ms	1	1	100.00
V2	tl_d_illegal_access	spi_device_tl_errors	4.080s	1.062ms	1	1	100.00
V2	tl_d_outstanding_access	spi_device_csr_hw_reset	0.830s	44.048us	1	1	100.00
		spi_device_csr_rw	1.360s	104.920us	1	1	100.00
		spi_device_csr_aliasing	11.450s	3.732ms	1	1	100.00
		spi_device_same_csr_outstanding	2.350s	135.977us	1	1	100.00
V2	tl_d_partial_access	spi_device_csr_hw_reset	0.830s	44.048us	1	1	100.00
		spi_device_csr_rw	1.360s	104.920us	1	1	100.00
		spi_device_csr_aliasing	11.450s	3.732ms	1	1	100.00
		spi_device_same_csr_outstanding	2.350s	135.977us	1	1	100.00
V2		TOTAL			22	22	100.00
V2S	tl_intg_err	spi_device_sec_cm	1.120s	240.258us	1	1	100.00
		spi_device_tl_intg_err	12.220s	1.489ms	1	1	100.00
V2S	sec_cm_bus_integrity	spi_device_tl_intg_err	12.220s	1.489ms	1	1	100.00
V2S		TOTAL			2	2	100.00
	Unmapped tests	spi_device_flash_mode_ignore_cmds	1.755m	49.607ms	1	1	100.00
		TOTAL			33	33	100.00