SRAM_CTRL/MAIN Simulation Results

Tuesday October 07 2025 19:21:11 UTC

GitHub Revision: 25151e0

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	20.760s	1.033ms	1	1	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	0.940s	46.445us	1	1	100.00
V1	csr_rw	sram_ctrl_csr_rw	1.010s	21.121us	1	1	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	1.600s	50.562us	1	1	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	1.060s	22.161us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	2.450s	716.924us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	1.010s	21.121us	1	1	100.00
		sram_ctrl_csr_aliasing	1.060s	22.161us	1	1	100.00
V1	mem_walk	sram_ctrl_mem_walk	1.899m	7.131ms	1	1	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	1.143m	2.905ms	1	1	100.00
V1		TOTAL			8	8	100.00
V2	multiple_keys	sram_ctrl_multiple_keys	4.019m	50.080ms	1	1	100.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	3.212m	4.105ms	1	1	100.00
V2	bijection	sram_ctrl_bijection	15.833m	35.465ms	1	1	100.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	6.340m	13.219ms	1	1	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	5.990s	1.027ms	1	1	100.00
V2	executable	sram_ctrl_executable	5.424m	27.432ms	1	1	100.00
V2	partial_access	sram_ctrl_partial_access	18.650s	1.682ms	1	1	100.00
		sram_ctrl_partial_access_b2b	4.384m	76.974ms	1	1	100.00
V2	max_throughput	sram_ctrl_max_throughput	15.940s	2.855ms	1	1	100.00
		sram_ctrl_throughput_w_partial_write	17.600s	737.515us	1	1	100.00
		sram_ctrl_throughput_w_readback	8.210s	2.837ms	1	1	100.00
V2	regwen	sram_ctrl_regwen	1.825m	3.327ms	1	1	100.00
V2	ram_cfg	sram_ctrl_ram_cfg	2.460s	483.054us	1	1	100.00
V2	stress_all	sram_ctrl_stress_all	56.812m	70.014ms	1	1	100.00
V2	alert_test	sram_ctrl_alert_test	0.750s	55.082us	1	1	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	3.060s	143.734us	1	1	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	3.060s	143.734us	1	1	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	0.940s	46.445us	1	1	100.00
		sram_ctrl_csr_rw	1.010s	21.121us	1	1	100.00
		sram_ctrl_csr_aliasing	1.060s	22.161us	1	1	100.00
		sram_ctrl_same_csr_outstanding	1.050s	24.764us	1	1	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	0.940s	46.445us	1	1	100.00
		sram_ctrl_csr_rw	1.010s	21.121us	1	1	100.00
		sram_ctrl_csr_aliasing	1.060s	22.161us	1	1	100.00
		sram_ctrl_same_csr_outstanding	1.050s	24.764us	1	1	100.00
V2		TOTAL			17	17	100.00
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	21.840s	15.423ms	1	1	100.00
V2S	tl_intg_err	sram_ctrl_sec_cm	0.750s	5.317us	0	1	0.00
		sram_ctrl_tl_intg_err	2.140s	382.431us	1	1	100.00
V2S	prim_count_check	sram_ctrl_sec_cm	0.750s	5.317us	0	1	0.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	2.140s	382.431us	1	1	100.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	1.825m	3.327ms	1	1	100.00
V2S	sec_cm_readback_config_regwen	sram_ctrl_regwen	1.825m	3.327ms	1	1	100.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	1.010s	21.121us	1	1	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	5.424m	27.432ms	1	1	100.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	5.424m	27.432ms	1	1	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	5.424m	27.432ms	1	1	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	5.990s	1.027ms	1	1	100.00
V2S	sec_cm_prim_ram_ctrl_mubi	sram_ctrl_mubi_enc_err	4.790s	2.678ms	1	1	100.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	21.840s	15.423ms	1	1	100.00
V2S	sec_cm_mem_readback	sram_ctrl_readback_err	4.170s	711.224us	1	1	100.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	20.760s	1.033ms	1	1	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	20.760s	1.033ms	1	1	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	5.424m	27.432ms	1	1	100.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	0.750s	5.317us	0	1	0.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	5.990s	1.027ms	1	1	100.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	0.750s	5.317us	0	1	0.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	0.750s	5.317us	0	1	0.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	20.760s	1.033ms	1	1	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	0.750s	5.317us	0	1	0.00
V2S		TOTAL			4	5	80.00
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	47.920s	2.540ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			30	31	96.77

Failure Buckets

• Offending '(!$isunknown(rdata_o))' has 1 failures:
  • Test sram_ctrl_sec_cm has 1 failures.

    • 0.sram_ctrl_sec_cm.14631714241044619995719194963851896309758832735082458121528755722318458693563
      Line 96, in log /nightly/current_run/scratch/master/sram_ctrl_main-sim-vcs/0.sram_ctrl_sec_cm/latest/run.log

            Offending '(!$isunknown(rdata_o))'
        UVM_ERROR @   5316923 ps: (prim_fifo_sync.sv:224) [ASSERT FAILED] DataKnown_A
        UVM_INFO @   5316923 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---