SRAM_CTRL/RET Simulation Results

Tuesday October 07 2025 19:21:11 UTC

GitHub Revision: 25151e0

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	16.720s	1.728ms	1	1	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	0.710s	14.544us	1	1	100.00
V1	csr_rw	sram_ctrl_csr_rw	0.670s	44.677us	1	1	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	1.600s	608.468us	1	1	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	0.650s	34.385us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	2.110s	47.541us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	0.670s	44.677us	1	1	100.00
		sram_ctrl_csr_aliasing	0.650s	34.385us	1	1	100.00
V1	mem_walk	sram_ctrl_mem_walk	8.100s	463.968us	1	1	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	3.690s	168.548us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	multiple_keys	sram_ctrl_multiple_keys	2.424m	10.560ms	1	1	100.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	2.650m	4.804ms	1	1	100.00
V2	bijection	sram_ctrl_bijection	42.470s	4.912ms	1	1	100.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	51.010s	407.612us	1	1	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	5.390s	1.095ms	1	1	100.00
V2	executable	sram_ctrl_executable	3.047m	3.738ms	1	1	100.00
V2	partial_access	sram_ctrl_partial_access	14.310s	4.601ms	1	1	100.00
		sram_ctrl_partial_access_b2b	1.710m	1.961ms	1	1	100.00
V2	max_throughput	sram_ctrl_max_throughput	35.970s	517.822us	1	1	100.00
		sram_ctrl_throughput_w_partial_write	41.960s	153.361us	1	1	100.00
		sram_ctrl_throughput_w_readback	32.070s	512.693us	1	1	100.00
V2	regwen	sram_ctrl_regwen	3.400m	7.103ms	1	1	100.00
V2	ram_cfg	sram_ctrl_ram_cfg	0.690s	79.576us	1	1	100.00
V2	stress_all	sram_ctrl_stress_all	14.640m	34.830ms	1	1	100.00
V2	alert_test	sram_ctrl_alert_test	0.660s	39.226us	1	1	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	2.940s	214.663us	1	1	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	2.940s	214.663us	1	1	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	0.710s	14.544us	1	1	100.00
		sram_ctrl_csr_rw	0.670s	44.677us	1	1	100.00
		sram_ctrl_csr_aliasing	0.650s	34.385us	1	1	100.00
		sram_ctrl_same_csr_outstanding	0.710s	25.344us	1	1	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	0.710s	14.544us	1	1	100.00
		sram_ctrl_csr_rw	0.670s	44.677us	1	1	100.00
		sram_ctrl_csr_aliasing	0.650s	34.385us	1	1	100.00
		sram_ctrl_same_csr_outstanding	0.710s	25.344us	1	1	100.00
V2		TOTAL			17	17	100.00
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	2.420s	1.997ms	1	1	100.00
V2S	tl_intg_err	sram_ctrl_sec_cm	0.660s	3.053us	0	1	0.00
		sram_ctrl_tl_intg_err	1.900s	334.739us	1	1	100.00
V2S	prim_count_check	sram_ctrl_sec_cm	0.660s	3.053us	0	1	0.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	1.900s	334.739us	1	1	100.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	3.400m	7.103ms	1	1	100.00
V2S	sec_cm_readback_config_regwen	sram_ctrl_regwen	3.400m	7.103ms	1	1	100.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	0.670s	44.677us	1	1	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	3.047m	3.738ms	1	1	100.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	3.047m	3.738ms	1	1	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	3.047m	3.738ms	1	1	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	5.390s	1.095ms	1	1	100.00
V2S	sec_cm_prim_ram_ctrl_mubi	sram_ctrl_mubi_enc_err	0.830s	39.478us	1	1	100.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	2.420s	1.997ms	1	1	100.00
V2S	sec_cm_mem_readback	sram_ctrl_readback_err	1.070s	69.212us	1	1	100.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	16.720s	1.728ms	1	1	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	16.720s	1.728ms	1	1	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	3.047m	3.738ms	1	1	100.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	0.660s	3.053us	0	1	0.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	5.390s	1.095ms	1	1	100.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	0.660s	3.053us	0	1	0.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	0.660s	3.053us	0	1	0.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	16.720s	1.728ms	1	1	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	0.660s	3.053us	0	1	0.00
V2S		TOTAL			4	5	80.00
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	1.258m	374.452us	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			30	31	96.77

Failure Buckets

• UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: * has 1 failures:
  • Test sram_ctrl_sec_cm has 1 failures.

    • 0.sram_ctrl_sec_cm.64506444291887739477796335790332134891385738855067646051897430123271772305165
      Line 96, in log /nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/0.sram_ctrl_sec_cm/latest/run.log

        UVM_ERROR @   3052860 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0
        UVM_INFO @   3052860 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---