SYSRST_CTRL Simulation Results

Tuesday October 07 2025 19:21:11 UTC

GitHub Revision: 25151e0

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke sysrst_ctrl_smoke 1.800s 2.121ms 1 1 100.00
V1 input_output_inverted sysrst_ctrl_in_out_inverted 5.350s 2.467ms 1 1 100.00
V1 combo_detect_ec_rst sysrst_ctrl_combo_detect_ec_rst 4.750s 2.204ms 1 1 100.00
V1 combo_detect_ec_rst_with_pre_cond sysrst_ctrl_combo_detect_ec_rst_with_pre_cond 3.110s 2.505ms 1 1 100.00
V1 csr_hw_reset sysrst_ctrl_csr_hw_reset 2.660s 4.017ms 1 1 100.00
V1 csr_rw sysrst_ctrl_csr_rw 1.620s 2.090ms 1 1 100.00
V1 csr_bit_bash sysrst_ctrl_csr_bit_bash 1.801m 39.073ms 1 1 100.00
V1 csr_aliasing sysrst_ctrl_csr_aliasing 4.410s 2.638ms 1 1 100.00
V1 csr_mem_rw_with_rand_reset sysrst_ctrl_csr_mem_rw_with_rand_reset 2.870s 2.052ms 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr sysrst_ctrl_csr_rw 1.620s 2.090ms 1 1 100.00
sysrst_ctrl_csr_aliasing 4.410s 2.638ms 1 1 100.00
V1 TOTAL 9 9 100.00
V2 combo_detect sysrst_ctrl_combo_detect 2.518m 81.985ms 1 1 100.00
V2 combo_detect_with_pre_cond sysrst_ctrl_combo_detect_with_pre_cond 1.111m 37.622ms 1 1 100.00
V2 auto_block_key_outputs sysrst_ctrl_auto_blk_key_output 7.150s 3.627ms 1 1 100.00
V2 keyboard_input_triggered_interrupt sysrst_ctrl_edge_detect 2.910s 4.950ms 1 1 100.00
V2 pin_output_keyboard_inversion_control sysrst_ctrl_pin_override_test 1.950s 2.523ms 1 1 100.00
V2 pin_input_value_accessibility sysrst_ctrl_pin_access_test 1.320s 2.190ms 1 1 100.00
V2 ec_power_on_reset sysrst_ctrl_ec_pwr_on_rst 4.040s 2.414ms 1 1 100.00
V2 flash_write_protect_output sysrst_ctrl_flash_wr_prot_out 3.290s 2.615ms 1 1 100.00
V2 ultra_low_power_test sysrst_ctrl_ultra_low_pwr 5.270s 4.199ms 1 1 100.00
V2 sysrst_ctrl_feature_disable sysrst_ctrl_feature_disable 1.173m 40.998ms 1 1 100.00
V2 stress_all sysrst_ctrl_stress_all 18.480s 9.926ms 1 1 100.00
V2 alert_test sysrst_ctrl_alert_test 1.020s 2.092ms 1 1 100.00
V2 intr_test sysrst_ctrl_intr_test 2.100s 2.030ms 1 1 100.00
V2 tl_d_oob_addr_access sysrst_ctrl_tl_errors 5.880s 2.033ms 1 1 100.00
V2 tl_d_illegal_access sysrst_ctrl_tl_errors 5.880s 2.033ms 1 1 100.00
V2 tl_d_outstanding_access sysrst_ctrl_csr_hw_reset 2.660s 4.017ms 1 1 100.00
sysrst_ctrl_csr_rw 1.620s 2.090ms 1 1 100.00
sysrst_ctrl_csr_aliasing 4.410s 2.638ms 1 1 100.00
sysrst_ctrl_same_csr_outstanding 25.960s 9.398ms 1 1 100.00
V2 tl_d_partial_access sysrst_ctrl_csr_hw_reset 2.660s 4.017ms 1 1 100.00
sysrst_ctrl_csr_rw 1.620s 2.090ms 1 1 100.00
sysrst_ctrl_csr_aliasing 4.410s 2.638ms 1 1 100.00
sysrst_ctrl_same_csr_outstanding 25.960s 9.398ms 1 1 100.00
V2 TOTAL 15 15 100.00
V2S tl_intg_err sysrst_ctrl_sec_cm 1.436m 42.011ms 1 1 100.00
sysrst_ctrl_tl_intg_err 5.670s 22.486ms 1 1 100.00
V2S sec_cm_bus_integrity sysrst_ctrl_tl_intg_err 5.670s 22.486ms 1 1 100.00
V2S TOTAL 2 2 100.00
V3 stress_all_with_rand_reset sysrst_ctrl_stress_all_with_rand_reset 6.470s 8.288ms 1 1 100.00
V3 TOTAL 1 1 100.00
TOTAL 27 27 100.00