UART Simulation Results

Tuesday October 07 2025 19:21:11 UTC

GitHub Revision: 25151e0

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	uart_smoke	10.350s	5.467ms	1	1	100.00
V1	csr_hw_reset	uart_csr_hw_reset	0.630s	56.962us	1	1	100.00
V1	csr_rw	uart_csr_rw	0.660s	31.111us	1	1	100.00
V1	csr_bit_bash	uart_csr_bit_bash	1.920s	212.916us	1	1	100.00
V1	csr_aliasing	uart_csr_aliasing	0.780s	26.730us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	uart_csr_mem_rw_with_rand_reset	0.850s	39.662us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	uart_csr_rw	0.660s	31.111us	1	1	100.00
		uart_csr_aliasing	0.780s	26.730us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	base_random_seq	uart_tx_rx	34.630s	94.397ms	1	1	100.00
V2	parity	uart_smoke	10.350s	5.467ms	1	1	100.00
		uart_tx_rx	34.630s	94.397ms	1	1	100.00
V2	parity_error	uart_intr	2.226m	454.508ms	1	1	100.00
		uart_rx_parity_err	43.030s	36.188ms	1	1	100.00
V2	watermark	uart_tx_rx	34.630s	94.397ms	1	1	100.00
		uart_intr	2.226m	454.508ms	1	1	100.00
V2	fifo_full	uart_fifo_full	1.918m	217.244ms	1	1	100.00
V2	fifo_overflow	uart_fifo_overflow	28.240s	87.263ms	1	1	100.00
V2	fifo_reset	uart_fifo_reset	40.620s	33.748ms	1	1	100.00
V2	rx_frame_err	uart_intr	2.226m	454.508ms	1	1	100.00
V2	rx_break_err	uart_intr	2.226m	454.508ms	1	1	100.00
V2	rx_timeout	uart_intr	2.226m	454.508ms	1	1	100.00
V2	perf	uart_perf	4.401m	24.624ms	1	1	100.00
V2	sys_loopback	uart_loopback	17.570s	11.382ms	1	1	100.00
V2	line_loopback	uart_loopback	17.570s	11.382ms	1	1	100.00
V2	rx_noise_filter	uart_noise_filter	6.630s	12.831ms	0	1	0.00
V2	rx_start_bit_filter	uart_rx_start_bit_filter	5.640s	4.254ms	1	1	100.00
V2	tx_overide	uart_tx_ovrd	1.790s	688.574us	1	1	100.00
V2	rx_oversample	uart_rx_oversample	2.260s	1.714ms	1	1	100.00
V2	long_b2b_transfer	uart_long_xfer_wo_dly	2.556m	105.073ms	1	1	100.00
V2	stress_all	uart_stress_all	22.924m	409.551ms	1	1	100.00
V2	alert_test	uart_alert_test	0.750s	22.077us	1	1	100.00
V2	intr_test	uart_intr_test	0.670s	12.406us	1	1	100.00
V2	tl_d_oob_addr_access	uart_tl_errors	1.400s	32.169us	1	1	100.00
V2	tl_d_illegal_access	uart_tl_errors	1.400s	32.169us	1	1	100.00
V2	tl_d_outstanding_access	uart_csr_hw_reset	0.630s	56.962us	1	1	100.00
		uart_csr_rw	0.660s	31.111us	1	1	100.00
		uart_csr_aliasing	0.780s	26.730us	1	1	100.00
		uart_same_csr_outstanding	0.800s	29.447us	1	1	100.00
V2	tl_d_partial_access	uart_csr_hw_reset	0.630s	56.962us	1	1	100.00
		uart_csr_rw	0.660s	31.111us	1	1	100.00
		uart_csr_aliasing	0.780s	26.730us	1	1	100.00
		uart_same_csr_outstanding	0.800s	29.447us	1	1	100.00
V2		TOTAL			17	18	94.44
V2S	tl_intg_err	uart_sec_cm	1.450s	216.533us	1	1	100.00
		uart_tl_intg_err	1.140s	50.039us	1	1	100.00
V2S	sec_cm_bus_integrity	uart_tl_intg_err	1.140s	50.039us	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	stress_all_with_rand_reset	uart_stress_all_with_rand_reset	30.250s	4.472ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			26	27	96.30

Failure Buckets

• UVM_ERROR (uart_scoreboard.sv:393) [scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (* [*] vs * [*]) check rx_idle fail: rx_en = *, uart_rx_clk_pulses = * has 1 failures:
  • Test uart_noise_filter has 1 failures.

    • 0.uart_noise_filter.59877259458958044985111941634706573601846499778436959076606425045654261093247
      Line 73, in log /nightly/current_run/scratch/master/uart-sim-vcs/0.uart_noise_filter/latest/run.log

        UVM_ERROR @ 12744567470 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
        UVM_ERROR @ 12820526411 ps: (uart_scoreboard.sv:377) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (0 [0x0] vs 1 [0x1]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 0
        UVM_ERROR @ 12820526411 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
        UVM_ERROR @ 12821026415 ps: (uart_scoreboard.sv:377) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (0 [0x0] vs 1 [0x1]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 0
        UVM_ERROR @ 12821026415 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0