CHIP Simulation Results

Tuesday October 07 2025 19:21:11 UTC

GitHub Revision: `25151e0`

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	chip_sw_example_tests	chip_sw_example_flash	2.152m	2.799ms	1	1	100.00
		chip_sw_example_rom	49.860s	1.833ms	1	1	100.00
		chip_sw_example_manufacturer	2.472m	2.611ms	1	1	100.00
		chip_sw_example_concurrency	3.431m	2.995ms	1	1	100.00
V1	csr_hw_reset	chip_csr_hw_reset	3.603m	5.717ms	1	1	100.00
V1	csr_rw	chip_csr_rw	3.159m	4.465ms	1	1	100.00
V1	csr_bit_bash	chip_csr_bit_bash	3.407m	4.177ms	1	1	100.00
V1	csr_aliasing	chip_csr_aliasing	55.391m	26.719ms	1	1	100.00
V1	csr_mem_rw_with_rand_reset	chip_csr_mem_rw_with_rand_reset	50.210s	3.069ms	0	1	0.00
V1	regwen_csr_and_corresponding_lockable_csr	chip_csr_aliasing	55.391m	26.719ms	1	1	100.00
		chip_csr_rw	3.159m	4.465ms	1	1	100.00
V1	xbar_smoke	xbar_smoke	8.830s	163.500us	1	1	100.00
V1	chip_sw_gpio_out	chip_sw_gpio	5.213m	4.171ms	1	1	100.00
V1	chip_sw_gpio_in	chip_sw_gpio	5.213m	4.171ms	1	1	100.00
V1	chip_sw_gpio_irq	chip_sw_gpio	5.213m	4.171ms	1	1	100.00
V1	chip_sw_uart_tx_rx	chip_sw_uart_tx_rx	5.583m	4.786ms	1	1	100.00
V1	chip_sw_uart_rx_overflow	chip_sw_uart_tx_rx	5.583m	4.786ms	1	1	100.00
		chip_sw_uart_tx_rx_idx1	5.081m	4.169ms	1	1	100.00
		chip_sw_uart_tx_rx_idx2	6.292m	4.468ms	1	1	100.00
		chip_sw_uart_tx_rx_idx3	5.663m	4.811ms	1	1	100.00
V1	chip_sw_uart_baud_rate	chip_sw_uart_rand_baudrate	17.857m	7.866ms	1	1	100.00
V1	chip_sw_uart_tx_rx_alt_clk_freq	chip_sw_uart_tx_rx_alt_clk_freq	6.153m	4.468ms	1	1	100.00
		chip_sw_uart_tx_rx_alt_clk_freq_low_speed	4.341m	4.361ms	1	1	100.00
V1		TOTAL			17	18	94.44
V2	chip_pin_mux	chip_padctrl_attributes	2.713m	5.139ms	1	1	100.00
V2	chip_padctrl_attributes	chip_padctrl_attributes	2.713m	5.139ms	1	1	100.00
V2	chip_sw_sleep_pin_mio_dio_val	chip_sw_sleep_pin_mio_dio_val	3.150m	3.278ms	1	1	100.00
V2	chip_sw_sleep_pin_wake	chip_sw_sleep_pin_wake	2.851m	2.354ms	0	1	0.00
V2	chip_sw_sleep_pin_retention	chip_sw_sleep_pin_retention	2.352m	4.167ms	1	1	100.00
V2	chip_sw_tap_strap_sampling	chip_tap_straps_dev	9.166m	8.483ms	1	1	100.00
		chip_tap_straps_testunlock0	7.286m	7.136ms	1	1	100.00
		chip_tap_straps_rma	3.903m	4.377ms	1	1	100.00
		chip_tap_straps_prod	14.966m	12.685ms	1	1	100.00
V2	chip_sw_pattgen_ios	chip_sw_pattgen_ios	3.059m	2.793ms	1	1	100.00
V2	chip_sw_sleep_pwm_pulses	chip_sw_sleep_pwm_pulses	15.161m	10.264ms	1	1	100.00
V2	chip_sw_data_integrity	chip_sw_data_integrity_escalation	7.672m	4.839ms	1	1	100.00
V2	chip_sw_instruction_integrity	chip_sw_data_integrity_escalation	7.672m	4.839ms	1	1	100.00
V2	chip_sw_ast_clk_outputs	chip_sw_ast_clk_outputs	9.712m	8.304ms	1	1	100.00
V2	chip_sw_ast_clk_rst_inputs	chip_sw_ast_clk_rst_inputs	45.376m	25.778ms	1	1	100.00
V2	chip_sw_ast_sys_clk_jitter	chip_sw_flash_ctrl_ops_jitter_en	6.317m	4.184ms	1	1	100.00
		chip_sw_flash_ctrl_access_jitter_en	9.613m	6.043ms	1	1	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en	55.457m	19.581ms	1	1	100.00
		chip_sw_aes_enc_jitter_en	2.709m	3.147ms	1	1	100.00
		chip_sw_edn_entropy_reqs_jitter	11.702m	6.083ms	1	1	100.00
		chip_sw_hmac_enc_jitter_en	2.891m	3.160ms	1	1	100.00
		chip_sw_keymgr_key_derivation_jitter_en	12.669m	7.971ms	1	1	100.00
		chip_sw_kmac_mode_kmac_jitter_en	2.516m	2.614ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	6.034m	4.373ms	1	1	100.00
		chip_sw_clkmgr_jitter	2.324m	3.560ms	1	1	100.00
V2	chip_sw_ast_usb_clk_calib	chip_sw_usb_ast_clk_calib	2.850m	2.577ms	1	1	100.00
V2	chip_sw_sensor_ctrl_ast_alerts	chip_sw_sensor_ctrl_alert	6.371m	5.887ms	1	1	100.00
		chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	4.873m	5.074ms	1	1	100.00
V2	chip_sw_sensor_ctrl_ast_status	chip_sw_sensor_ctrl_status	1.851m	2.126ms	1	1	100.00
V2	chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	4.873m	5.074ms	1	1	100.00
V2	chip_sw_smoketest	chip_sw_flash_scrambling_smoketest	3.083m	2.635ms	1	1	100.00
		chip_sw_aes_smoketest	2.514m	2.716ms	1	1	100.00
		chip_sw_aon_timer_smoketest	2.741m	2.904ms	1	1	100.00
		chip_sw_clkmgr_smoketest	2.230m	2.637ms	1	1	100.00
		chip_sw_csrng_smoketest	2.377m	2.439ms	1	1	100.00
		chip_sw_entropy_src_smoketest	12.761m	7.029ms	1	1	100.00
		chip_sw_gpio_smoketest	3.459m	3.647ms	1	1	100.00
		chip_sw_hmac_smoketest	3.475m	3.181ms	1	1	100.00
		chip_sw_kmac_smoketest	2.712m	3.107ms	1	1	100.00
		chip_sw_otbn_smoketest	17.188m	9.034ms	1	1	100.00
		chip_sw_pwrmgr_smoketest	3.069m	5.614ms	1	1	100.00
		chip_sw_pwrmgr_usbdev_smoketest	3.897m	6.276ms	1	1	100.00
		chip_sw_rv_plic_smoketest	3.216m	3.132ms	1	1	100.00
		chip_sw_rv_timer_smoketest	2.723m	2.792ms	1	1	100.00
		chip_sw_rstmgr_smoketest	2.372m	2.393ms	1	1	100.00
		chip_sw_sram_ctrl_smoketest	2.218m	3.186ms	1	1	100.00
		chip_sw_uart_smoketest	1.855m	2.486ms	1	1	100.00
V2	chip_sw_otp_smoketest	chip_sw_otp_ctrl_smoketest	3.117m	2.759ms	1	1	100.00
V2	chip_sw_rom_functests	rom_keymgr_functest	5.625m	4.683ms	1	1	100.00
V2	chip_sw_boot	chip_sw_uart_tx_rx_bootstrap	2.182h	60.583ms	1	1	100.00
V2	chip_sw_secure_boot	rom_e2e_smoke	41.330m	15.024ms	1	1	100.00
V2	chip_sw_rom_raw_unlock	rom_raw_unlock	2.915m	5.920ms	1	1	100.00
V2	chip_sw_power_idle_load	chip_sw_power_idle_load	2.961m	3.134ms	0	1	0.00
V2	chip_sw_power_sleep_load	chip_sw_power_sleep_load	2.453m	3.344ms	0	1	0.00
V2	chip_sw_exit_test_unlocked_bootstrap	chip_sw_exit_test_unlocked_bootstrap	1.958h	52.995ms	1	1	100.00
V2	chip_sw_inject_scramble_seed	chip_sw_inject_scramble_seed	2.084h	56.062ms	1	1	100.00
V2	tl_d_oob_addr_access	chip_tl_errors	59.160s	2.263ms	0	1	0.00
V2	tl_d_illegal_access	chip_tl_errors	59.160s	2.263ms	0	1	0.00
V2	tl_d_outstanding_access	chip_csr_aliasing	55.391m	26.719ms	1	1	100.00
		chip_same_csr_outstanding	49.609m	31.562ms	1	1	100.00
		chip_csr_hw_reset	3.603m	5.717ms	1	1	100.00
		chip_csr_rw	3.159m	4.465ms	1	1	100.00
V2	tl_d_partial_access	chip_csr_aliasing	55.391m	26.719ms	1	1	100.00
		chip_same_csr_outstanding	49.609m	31.562ms	1	1	100.00
		chip_csr_hw_reset	3.603m	5.717ms	1	1	100.00
		chip_csr_rw	3.159m	4.465ms	1	1	100.00
V2	xbar_base_random_sequence	xbar_random	45.850s	2.074ms	1	1	100.00
V2	xbar_random_delay	xbar_smoke_zero_delays	4.710s	38.614us	1	1	100.00
		xbar_smoke_large_delays	52.400s	8.955ms	1	1	100.00
		xbar_smoke_slow_rsp	45.470s	5.239ms	1	1	100.00
		xbar_random_zero_delays	20.720s	269.166us	1	1	100.00
		xbar_random_large_delays	3.930m	40.419ms	1	1	100.00
		xbar_random_slow_rsp	1.153m	7.358ms	1	1	100.00
V2	xbar_unmapped_address	xbar_unmapped_addr	21.800s	304.500us	1	1	100.00
		xbar_error_and_unmapped_addr	30.390s	1.199ms	1	1	100.00
V2	xbar_error_cases	xbar_error_random	26.410s	1.265ms	1	1	100.00
		xbar_error_and_unmapped_addr	30.390s	1.199ms	1	1	100.00
V2	xbar_all_access_same_device	xbar_access_same_device	11.890s	299.733us	1	1	100.00
		xbar_access_same_device_slow_rsp	1.916m	13.028ms	1	1	100.00
V2	xbar_all_hosts_use_same_source_id	xbar_same_source	17.780s	921.336us	1	1	100.00
V2	xbar_stress_all	xbar_stress_all	2.266m	3.404ms	1	1	100.00
		xbar_stress_all_with_error	8.310s	96.112us	1	1	100.00
V2	xbar_stress_with_reset	xbar_stress_all_with_rand_reset	9.144m	17.989ms	1	1	100.00
		xbar_stress_all_with_reset_error	2.987m	3.324ms	1	1	100.00
V2	rom_e2e_smoke	rom_e2e_smoke	41.330m	15.024ms	1	1	100.00
V2	rom_e2e_shutdown_output	rom_e2e_shutdown_output	41.444m	31.955ms	1	1	100.00
V2	rom_e2e_shutdown_exception_c	rom_e2e_shutdown_exception_c	43.046m	15.126ms	1	1	100.00
V2	rom_e2e_boot_policy_valid	rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0	34.545m	11.670ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_dev	43.504m	17.297ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod	44.836m	16.201ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod_end	43.234m	17.408ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_rma	42.163m	14.912ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0	18.010s	10.180us	0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_dev	19.690s	10.280us	0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod	17.930s	10.360us	0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod_end	17.340s	10.360us	0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_rma	17.510s	10.240us	0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0	17.020s	10.220us	0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_dev	16.950s	10.240us	0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod	16.650s	10.380us	0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod_end	18.140s	10.400us	0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_rma	17.050s	10.340us	0	1	0.00
V2	rom_e2e_sigverify_always	rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0	16.610s	10.220us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_dev	17.230s	10.120us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod	16.500s	10.340us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod_end	16.630s	10.340us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_rma	21.500s	10.240us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0	15.930s	10.260us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_dev	17.360s	10.140us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod	17.880s	10.220us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod_end	21.290s	10.220us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_rma	18.000s	10.240us	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0	17.940s	10.300us	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_dev	22.550s	10.200us	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod	20.930s	10.320us	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod_end	17.230s	10.100us	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_rma	18.680s	10.240us	0	1	0.00
V2	rom_e2e_asm_init	rom_e2e_asm_init_test_unlocked0	33.131m	10.999ms	1	1	100.00
		rom_e2e_asm_init_dev	41.472m	15.261ms	1	1	100.00
		rom_e2e_asm_init_prod	42.939m	17.117ms	1	1	100.00
		rom_e2e_asm_init_prod_end	43.061m	16.021ms	1	1	100.00
		rom_e2e_asm_init_rma	40.552m	15.387ms	1	1	100.00
V2	rom_e2e_keymgr_init	rom_e2e_keymgr_init_rom_ext_meas	41.089m	15.241ms	1	1	100.00
		rom_e2e_keymgr_init_rom_ext_no_meas	40.355m	15.539ms	1	1	100.00
		rom_e2e_keymgr_init_rom_ext_invalid_meas	39.582m	15.351ms	1	1	100.00
V2	rom_e2e_static_critical	rom_e2e_static_critical	41.450m	18.999ms	1	1	100.00
V2	chip_sw_adc_ctrl_debug_cable_irq	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	50.809m	34.359ms	0	1	0.00
V2	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	50.809m	34.359ms	0	1	0.00
V2	chip_sw_aes_enc	chip_sw_aes_enc	3.091m	2.829ms	1	1	100.00
		chip_sw_aes_enc_jitter_en	2.709m	3.147ms	1	1	100.00
V2	chip_sw_aes_entropy	chip_sw_aes_entropy	2.018m	2.382ms	1	1	100.00
V2	chip_sw_aes_idle	chip_sw_aes_idle	2.212m	2.929ms	1	1	100.00
V2	chip_sw_aes_sideload	chip_sw_keymgr_sideload_aes	22.832m	10.175ms	1	1	100.00
V2	chip_sw_alert_handler_alerts	chip_sw_alert_test	3.112m	3.009ms	0	1	0.00
V2	chip_sw_alert_handler_escalations	chip_sw_alert_handler_escalation	4.835m	4.833ms	1	1	100.00
V2	chip_sw_all_escalation_resets	chip_sw_all_escalation_resets	7.186m	6.141ms	1	1	100.00
V2	chip_sw_alert_handler_irqs	chip_plic_all_irqs_0	9.462m	5.123ms	1	1	100.00
		chip_plic_all_irqs_10	4.685m	3.654ms	1	1	100.00
		chip_plic_all_irqs_20	6.365m	4.140ms	1	1	100.00
V2	chip_sw_alert_handler_entropy	chip_sw_alert_handler_entropy	2.475m	3.034ms	1	1	100.00
V2	chip_sw_alert_handler_crashdump	chip_sw_rstmgr_alert_info	16.808m	12.753ms	1	1	100.00
V2	chip_sw_alert_handler_ping_timeout	chip_sw_alert_handler_ping_timeout	5.443m	4.773ms	1	1	100.00
V2	chip_sw_alert_handler_lpg_sleep_mode_alerts	chip_sw_alert_handler_lpg_sleep_mode_alerts	2.297m	2.545ms	0	1	0.00
V2	chip_sw_alert_handler_lpg_sleep_mode_pings	chip_sw_alert_handler_lpg_sleep_mode_pings			0	1	0.00
V2	chip_sw_alert_handler_lpg_clock_off	chip_sw_alert_handler_lpg_clkoff	13.704m	6.343ms	1	1	100.00
V2	chip_sw_alert_handler_lpg_reset_toggle	chip_sw_alert_handler_lpg_reset_toggle	16.727m	8.030ms	1	1	100.00
V2	chip_sw_alert_handler_ping_ok	chip_sw_alert_handler_ping_ok	14.345m	7.867ms	1	1	100.00
V2	chip_sw_alert_handler_reverse_ping_in_deep_sleep	chip_sw_alert_handler_reverse_ping_in_deep_sleep	2.111h	255.449ms	1	1	100.00
V2	chip_sw_aon_timer_wakeup_irq	chip_sw_aon_timer_irq	4.157m	3.786ms	1	1	100.00
V2	chip_sw_aon_timer_sleep_wakeup	chip_sw_pwrmgr_smoketest	3.069m	5.614ms	1	1	100.00
V2	chip_sw_aon_timer_wdog_bark_irq	chip_sw_aon_timer_irq	4.157m	3.786ms	1	1	100.00
V2	chip_sw_aon_timer_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	7.903m	9.331ms	1	1	100.00
V2	chip_sw_aon_timer_sleep_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	7.903m	9.331ms	1	1	100.00
V2	chip_sw_aon_timer_sleep_wdog_sleep_pause	chip_sw_aon_timer_sleep_wdog_sleep_pause	3.069m	6.335ms	1	1	100.00
V2	chip_sw_aon_timer_wdog_lc_escalate	chip_sw_aon_timer_wdog_lc_escalate	6.477m	5.650ms	1	1	100.00
V2	chip_sw_clkmgr_idle_trans	chip_sw_otbn_randomness	9.173m	5.386ms	1	1	100.00
		chip_sw_aes_idle	2.212m	2.929ms	1	1	100.00
		chip_sw_hmac_enc_idle	3.046m	3.309ms	1	1	100.00
		chip_sw_kmac_idle	2.289m	2.913ms	1	1	100.00
V2	chip_sw_clkmgr_off_trans	chip_sw_clkmgr_off_aes_trans	3.311m	3.809ms	1	1	100.00
		chip_sw_clkmgr_off_hmac_trans	5.074m	4.506ms	1	1	100.00
		chip_sw_clkmgr_off_kmac_trans	4.771m	5.021ms	1	1	100.00
		chip_sw_clkmgr_off_otbn_trans	4.407m	5.166ms	1	1	100.00
V2	chip_sw_clkmgr_off_peri	chip_sw_clkmgr_off_peri	9.748m	11.299ms	1	1	100.00
V2	chip_sw_clkmgr_div	chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	5.924m	3.845ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	6.119m	4.622ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	5.473m	3.464ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	6.193m	5.012ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	6.193m	3.498ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	5.985m	4.474ms	1	1	100.00
		chip_sw_ast_clk_outputs	9.712m	8.304ms	1	1	100.00
V2	chip_sw_clkmgr_external_clk_src_for_lc	chip_sw_clkmgr_external_clk_src_for_lc	8.021m	8.564ms	1	1	100.00
V2	chip_sw_clkmgr_external_clk_src_for_sw	chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	5.473m	3.464ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	6.193m	5.012ms	1	1	100.00
V2	chip_sw_clkmgr_jitter	chip_sw_flash_ctrl_ops_jitter_en	6.317m	4.184ms	1	1	100.00
		chip_sw_flash_ctrl_access_jitter_en	9.613m	6.043ms	1	1	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en	55.457m	19.581ms	1	1	100.00
		chip_sw_aes_enc_jitter_en	2.709m	3.147ms	1	1	100.00
		chip_sw_edn_entropy_reqs_jitter	11.702m	6.083ms	1	1	100.00
		chip_sw_hmac_enc_jitter_en	2.891m	3.160ms	1	1	100.00
		chip_sw_keymgr_key_derivation_jitter_en	12.669m	7.971ms	1	1	100.00
		chip_sw_kmac_mode_kmac_jitter_en	2.516m	2.614ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	6.034m	4.373ms	1	1	100.00
		chip_sw_clkmgr_jitter	2.324m	3.560ms	1	1	100.00
V2	chip_sw_clkmgr_extended_range	chip_sw_clkmgr_jitter_reduced_freq	1.603m	2.274ms	1	1	100.00
		chip_sw_flash_ctrl_ops_jitter_en_reduced_freq	6.719m	4.672ms	1	1	100.00
		chip_sw_flash_ctrl_access_jitter_en_reduced_freq	10.772m	6.992ms	1	1	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq	52.518m	25.048ms	1	1	100.00
		chip_sw_aes_enc_jitter_en_reduced_freq	2.664m	2.770ms	1	1	100.00
		chip_sw_hmac_enc_jitter_en_reduced_freq	2.727m	3.542ms	1	1	100.00
		chip_sw_keymgr_key_derivation_jitter_en_reduced_freq	20.441m	12.105ms	1	1	100.00
		chip_sw_kmac_mode_kmac_jitter_en_reduced_freq	3.081m	3.409ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq	5.676m	5.163ms	1	1	100.00
		chip_sw_flash_init_reduced_freq	18.144m	20.638ms	1	1	100.00
		chip_sw_csrng_edn_concurrency_reduced_freq	2.785h	127.706ms	1	1	100.00
V2	chip_sw_clkmgr_deep_sleep_frequency	chip_sw_ast_clk_outputs	9.712m	8.304ms	1	1	100.00
V2	chip_sw_clkmgr_sleep_frequency	chip_sw_clkmgr_sleep_frequency	5.809m	4.076ms	1	1	100.00
V2	chip_sw_clkmgr_reset_frequency	chip_sw_clkmgr_reset_frequency	3.976m	3.182ms	1	1	100.00
V2	chip_sw_clkmgr_escalation_reset	chip_sw_all_escalation_resets	7.186m	6.141ms	1	1	100.00
V2	chip_sw_clkmgr_alert_handler_clock_enables	chip_sw_alert_handler_lpg_clkoff	13.704m	6.343ms	1	1	100.00
V2	chip_sw_csrng_edn_cmd	chip_sw_entropy_src_csrng	16.190m	8.113ms	1	1	100.00
V2	chip_sw_csrng_fuse_en_sw_app_read	chip_sw_csrng_fuse_en_sw_app_read_test	3.090m	3.624ms	1	1	100.00
V2	chip_sw_csrng_lc_hw_debug_en	chip_sw_csrng_lc_hw_debug_en_test	6.247m	5.720ms	1	1	100.00
V2	chip_sw_csrng_known_answer_tests	chip_sw_csrng_kat_test	2.621m	3.102ms	1	1	100.00
V2	chip_sw_edn_entropy_reqs	chip_sw_csrng_edn_concurrency	49.183m	17.545ms	1	1	100.00
		chip_sw_entropy_src_ast_rng_req	2.378m	2.772ms	1	1	100.00
		chip_sw_edn_entropy_reqs	12.413m	7.368ms	1	1	100.00
V2	chip_sw_entropy_src_ast_rng_req	chip_sw_entropy_src_ast_rng_req	2.378m	2.772ms	1	1	100.00
V2	chip_sw_entropy_src_csrng	chip_sw_entropy_src_csrng	16.190m	8.113ms	1	1	100.00
V2	chip_sw_entropy_src_known_answer_tests	chip_sw_entropy_src_kat_test	2.737m	3.136ms	1	1	100.00
V2	chip_sw_flash_init	chip_sw_flash_init	19.562m	19.786ms	1	1	100.00
V2	chip_sw_flash_host_access	chip_sw_flash_ctrl_access	10.102m	5.028ms	1	1	100.00
		chip_sw_flash_ctrl_access_jitter_en	9.613m	6.043ms	1	1	100.00
V2	chip_sw_flash_ctrl_ops	chip_sw_flash_ctrl_ops	5.662m	4.536ms	1	1	100.00
		chip_sw_flash_ctrl_ops_jitter_en	6.317m	4.184ms	1	1	100.00
V2	chip_sw_flash_rma_unlocked	chip_sw_flash_rma_unlocked	1.052h	44.687ms	1	1	100.00
V2	chip_sw_flash_scramble	chip_sw_flash_init	19.562m	19.786ms	1	1	100.00
V2	chip_sw_flash_idle_low_power	chip_sw_flash_ctrl_idle_low_power	2.733m	3.281ms	1	1	100.00
V2	chip_sw_flash_keymgr_seeds	chip_sw_keymgr_key_derivation	11.656m	7.088ms	1	1	100.00
V2	chip_sw_flash_lc_creator_seed_sw_rw_en	chip_sw_flash_ctrl_lc_rw_en	4.716m	4.965ms	1	1	100.00
V2	chip_sw_flash_creator_seed_wipe_on_rma	chip_sw_flash_rma_unlocked	1.052h	44.687ms	1	1	100.00
V2	chip_sw_flash_lc_owner_seed_sw_rw_en	chip_sw_flash_ctrl_lc_rw_en	4.716m	4.965ms	1	1	100.00
V2	chip_sw_flash_lc_iso_part_sw_rd_en	chip_sw_flash_ctrl_lc_rw_en	4.716m	4.965ms	1	1	100.00
V2	chip_sw_flash_lc_iso_part_sw_wr_en	chip_sw_flash_ctrl_lc_rw_en	4.716m	4.965ms	1	1	100.00
V2	chip_sw_flash_lc_seed_hw_rd_en	chip_sw_flash_ctrl_lc_rw_en	4.716m	4.965ms	1	1	100.00
V2	chip_sw_flash_lc_escalate_en	chip_sw_all_escalation_resets	7.186m	6.141ms	1	1	100.00
V2	chip_sw_flash_prim_tl_access	chip_prim_tl_access	1.812m	4.236ms	1	1	100.00
V2	chip_sw_flash_ctrl_clock_freqs	chip_sw_flash_ctrl_clock_freqs	8.303m	5.159ms	1	1	100.00
V2	chip_sw_flash_ctrl_escalation_reset	chip_sw_flash_crash_alert	5.793m	5.330ms	1	1	100.00
V2	chip_sw_flash_ctrl_write_clear	chip_sw_flash_crash_alert	5.793m	5.330ms	1	1	100.00
V2	chip_sw_hmac_enc	chip_sw_hmac_enc	2.098m	2.852ms	1	1	100.00
		chip_sw_hmac_enc_jitter_en	2.891m	3.160ms	1	1	100.00
V2	chip_sw_hmac_idle	chip_sw_hmac_enc_idle	3.046m	3.309ms	1	1	100.00
V2	chip_sw_hmac_all_configurations	chip_sw_hmac_oneshot	2.725m	2.684ms	0	1	0.00
V2	chip_sw_hmac_multistream_mode	chip_sw_hmac_multistream	6.192m	3.691ms	1	1	100.00
V2	chip_sw_i2c_host_tx_rx	chip_sw_i2c_host_tx_rx	8.132m	5.299ms	1	1	100.00
		chip_sw_i2c_host_tx_rx_idx1	6.478m	5.349ms	1	1	100.00
		chip_sw_i2c_host_tx_rx_idx2	5.595m	4.861ms	1	1	100.00
V2	chip_sw_i2c_device_tx_rx	chip_sw_i2c_device_tx_rx	4.686m	4.287ms	1	1	100.00
V2	chip_sw_keymgr_key_derivation	chip_sw_keymgr_key_derivation	11.656m	7.088ms	1	1	100.00
		chip_sw_keymgr_key_derivation_jitter_en	12.669m	7.971ms	1	1	100.00
V2	chip_sw_keymgr_sideload_kmac	chip_sw_keymgr_sideload_kmac	13.418m	6.918ms	1	1	100.00
V2	chip_sw_keymgr_sideload_aes	chip_sw_keymgr_sideload_aes	22.832m	10.175ms	1	1	100.00
V2	chip_sw_keymgr_sideload_otbn	chip_sw_keymgr_sideload_otbn	43.701m	14.148ms	1	1	100.00
V2	chip_sw_kmac_enc	chip_sw_kmac_mode_cshake	2.885m	3.333ms	1	1	100.00
		chip_sw_kmac_mode_kmac	2.889m	2.839ms	1	1	100.00
		chip_sw_kmac_mode_kmac_jitter_en	2.516m	2.614ms	1	1	100.00
V2	chip_sw_kmac_app_keymgr	chip_sw_keymgr_key_derivation	11.656m	7.088ms	1	1	100.00
V2	chip_sw_kmac_app_lc	chip_sw_lc_ctrl_transition	6.345m	6.982ms	1	1	100.00
V2	chip_sw_kmac_app_rom	chip_sw_kmac_app_rom	2.662m	2.720ms	1	1	100.00
V2	chip_sw_kmac_entropy	chip_sw_kmac_entropy	20.764m	9.243ms	1	1	100.00
V2	chip_sw_kmac_idle	chip_sw_kmac_idle	2.289m	2.913ms	1	1	100.00
V2	chip_sw_lc_ctrl_alert_handler_escalation	chip_sw_alert_handler_escalation	4.835m	4.833ms	1	1	100.00
V2	chip_sw_lc_ctrl_jtag_access	chip_tap_straps_dev	9.166m	8.483ms	1	1	100.00
		chip_tap_straps_rma	3.903m	4.377ms	1	1	100.00
		chip_tap_straps_prod	14.966m	12.685ms	1	1	100.00
V2	chip_sw_lc_ctrl_otp_hw_cfg0	chip_sw_lc_ctrl_otp_hw_cfg0	2.178m	2.613ms	1	1	100.00
V2	chip_sw_lc_ctrl_init	chip_sw_lc_ctrl_transition	6.345m	6.982ms	1	1	100.00
V2	chip_sw_lc_ctrl_transitions	chip_sw_lc_ctrl_transition	6.345m	6.982ms	1	1	100.00
V2	chip_sw_lc_ctrl_kmac_req	chip_sw_lc_ctrl_transition	6.345m	6.982ms	1	1	100.00
V2	chip_sw_lc_ctrl_key_div	chip_sw_keymgr_key_derivation_prod	23.841m	10.889ms	1	1	100.00
V2	chip_sw_lc_ctrl_broadcast	chip_sw_flash_ctrl_lc_rw_en	4.716m	4.965ms	1	1	100.00
		chip_sw_flash_rma_unlocked	1.052h	44.687ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_test_unlocked0	3.389m	3.121ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_dev	9.375m	7.508ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_prod	7.604m	5.647ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_rma	9.342m	5.879ms	1	1	100.00
		chip_sw_lc_ctrl_transition	6.345m	6.982ms	1	1	100.00
		chip_sw_keymgr_key_derivation	11.656m	7.088ms	1	1	100.00
		chip_sw_rom_ctrl_integrity_check	5.473m	9.902ms	1	1	100.00
		chip_sw_sram_ctrl_execution_main	9.690m	8.746ms	1	1	100.00
		chip_prim_tl_access	1.812m	4.236ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_lc	8.021m	8.564ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	5.924m	3.845ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	6.119m	4.622ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	5.473m	3.464ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	6.193m	5.012ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	6.193m	3.498ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	5.985m	4.474ms	1	1	100.00
		chip_tap_straps_dev	9.166m	8.483ms	1	1	100.00
		chip_tap_straps_rma	3.903m	4.377ms	1	1	100.00
		chip_tap_straps_prod	14.966m	12.685ms	1	1	100.00
		chip_rv_dm_lc_disabled	2.827m	8.038ms	1	1	100.00
V2	chip_lc_scrap	chip_sw_lc_ctrl_rma_to_scrap	3.090m	2.999ms	1	1	100.00
		chip_sw_lc_ctrl_raw_to_scrap	1.300m	2.863ms	1	1	100.00
		chip_sw_lc_ctrl_test_locked0_to_scrap	1.701m	3.481ms	1	1	100.00
		chip_sw_lc_ctrl_rand_to_scrap	1.447m	3.564ms	1	1	100.00
V2	chip_lc_test_locked	chip_sw_lc_walkthrough_testunlocks	19.942m	27.907ms	1	1	100.00
		chip_rv_dm_lc_disabled	2.827m	8.038ms	1	1	100.00
V2	chip_sw_lc_walkthrough	chip_sw_lc_walkthrough_dev	1.093h	47.175ms	1	1	100.00
		chip_sw_lc_walkthrough_prod	1.061h	45.546ms	1	1	100.00
		chip_sw_lc_walkthrough_prodend	10.100m	11.075ms	1	1	100.00
		chip_sw_lc_walkthrough_rma	1.153h	46.676ms	1	1	100.00
		chip_sw_lc_walkthrough_testunlocks	19.942m	27.907ms	1	1	100.00
V2	chip_sw_lc_ctrl_volatile_raw_unlock	chip_sw_lc_ctrl_volatile_raw_unlock	55.920s	2.311ms	1	1	100.00
		chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz	1.207m	2.653ms	1	1	100.00
		rom_volatile_raw_unlock	1.166m	2.679ms	1	1	100.00
V2	chip_sw_otbn_op	chip_sw_otbn_ecdsa_op_irq	55.029m	16.672ms	1	1	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en	55.457m	19.581ms	1	1	100.00
V2	chip_sw_otbn_rnd_entropy	chip_sw_otbn_randomness	9.173m	5.386ms	1	1	100.00
V2	chip_sw_otbn_urnd_entropy	chip_sw_otbn_randomness	9.173m	5.386ms	1	1	100.00
V2	chip_sw_otbn_idle	chip_sw_otbn_randomness	9.173m	5.386ms	1	1	100.00
V2	chip_sw_otbn_mem_scramble	chip_sw_otbn_mem_scramble	4.504m	3.407ms	1	1	100.00
V2	chip_otp_ctrl_init	chip_sw_lc_ctrl_transition	6.345m	6.982ms	1	1	100.00
V2	chip_sw_otp_ctrl_keys	chip_sw_flash_init	19.562m	19.786ms	1	1	100.00
		chip_sw_otbn_mem_scramble	4.504m	3.407ms	1	1	100.00
		chip_sw_keymgr_key_derivation	11.656m	7.088ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access	5.188m	3.909ms	1	1	100.00
		chip_sw_rv_core_ibex_icache_invalidate	2.557m	2.550ms	1	1	100.00
V2	chip_sw_otp_ctrl_entropy	chip_sw_flash_init	19.562m	19.786ms	1	1	100.00
		chip_sw_otbn_mem_scramble	4.504m	3.407ms	1	1	100.00
		chip_sw_keymgr_key_derivation	11.656m	7.088ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access	5.188m	3.909ms	1	1	100.00
		chip_sw_rv_core_ibex_icache_invalidate	2.557m	2.550ms	1	1	100.00
V2	chip_sw_otp_ctrl_program	chip_sw_lc_ctrl_transition	6.345m	6.982ms	1	1	100.00
V2	chip_sw_otp_ctrl_program_error	chip_sw_lc_ctrl_program_error	5.469m	5.156ms	1	1	100.00
V2	chip_sw_otp_ctrl_hw_cfg0	chip_sw_lc_ctrl_otp_hw_cfg0	2.178m	2.613ms	1	1	100.00
V2	chip_sw_otp_ctrl_lc_signals	chip_sw_otp_ctrl_lc_signals_test_unlocked0	3.389m	3.121ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_dev	9.375m	7.508ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_prod	7.604m	5.647ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_rma	9.342m	5.879ms	1	1	100.00
		chip_sw_lc_ctrl_transition	6.345m	6.982ms	1	1	100.00
		chip_prim_tl_access	1.812m	4.236ms	1	1	100.00
V2	chip_sw_otp_prim_tl_access	chip_prim_tl_access	1.812m	4.236ms	1	1	100.00
V2	chip_sw_otp_ctrl_dai_lock	chip_sw_otp_ctrl_dai_lock	18.158m	9.020ms	1	1	100.00
V2	chip_sw_pwrmgr_external_full_reset	chip_sw_pwrmgr_full_aon_reset	5.466m	8.282ms	1	1	100.00
V2	chip_sw_pwrmgr_random_sleep_all_wake_ups	chip_sw_pwrmgr_random_sleep_all_wake_ups	22.720m	27.151ms	1	1	100.00
V2	chip_sw_pwrmgr_normal_sleep_all_wake_ups	chip_sw_pwrmgr_normal_sleep_all_wake_ups	4.718m	7.611ms	1	1	100.00
V2	chip_sw_pwrmgr_deep_sleep_por_reset	chip_sw_pwrmgr_deep_sleep_por_reset	7.928m	7.822ms	1	1	100.00
V2	chip_sw_pwrmgr_normal_sleep_por_reset	chip_sw_pwrmgr_normal_sleep_por_reset	4.915m	7.591ms	1	1	100.00
V2	chip_sw_pwrmgr_deep_sleep_all_wake_ups	chip_sw_pwrmgr_deep_sleep_all_wake_ups	13.559m	21.489ms	1	1	100.00
V2	chip_sw_pwrmgr_deep_sleep_all_reset_reqs	chip_sw_pwrmgr_deep_sleep_all_reset_reqs	15.427m	16.691ms	1	1	100.00
		chip_sw_aon_timer_wdog_bite_reset	7.903m	9.331ms	1	1	100.00
V2	chip_sw_pwrmgr_normal_sleep_all_reset_reqs	chip_sw_pwrmgr_normal_sleep_all_reset_reqs	11.807m	10.991ms	1	1	100.00
V2	chip_sw_pwrmgr_wdog_reset	chip_sw_pwrmgr_wdog_reset	6.501m	5.014ms	1	1	100.00
V2	chip_sw_pwrmgr_aon_power_glitch_reset	chip_sw_pwrmgr_full_aon_reset	5.466m	8.282ms	1	1	100.00
V2	chip_sw_pwrmgr_main_power_glitch_reset	chip_sw_pwrmgr_main_power_glitch_reset	3.158m	4.186ms	1	1	100.00
V2	chip_sw_pwrmgr_random_sleep_power_glitch_reset	chip_sw_pwrmgr_random_sleep_power_glitch_reset	32.187m	27.173ms	1	1	100.00
V2	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	5.093m	6.969ms	1	1	100.00
V2	chip_sw_pwrmgr_sleep_power_glitch_reset	chip_sw_pwrmgr_sleep_power_glitch_reset	5.942m	6.489ms	1	1	100.00
V2	chip_sw_pwrmgr_random_sleep_all_reset_reqs	chip_sw_pwrmgr_random_sleep_all_reset_reqs	26.515m	23.132ms	1	1	100.00
V2	chip_sw_pwrmgr_sysrst_ctrl_reset	chip_sw_pwrmgr_sysrst_ctrl_reset	10.187m	6.697ms	1	1	100.00
		chip_sw_pwrmgr_all_reset_reqs	19.613m	11.119ms	1	1	100.00
V2	chip_sw_pwrmgr_b2b_sleep_reset_req	chip_sw_pwrmgr_b2b_sleep_reset_req	23.317m	27.580ms	1	1	100.00
V2	chip_sw_pwrmgr_sleep_disabled	chip_sw_pwrmgr_sleep_disabled	2.443m	2.561ms	1	1	100.00
V2	chip_sw_pwrmgr_escalation_reset	chip_sw_all_escalation_resets	7.186m	6.141ms	1	1	100.00
V2	chip_sw_rom_access	chip_sw_rom_ctrl_integrity_check	5.473m	9.902ms	1	1	100.00
V2	chip_sw_rom_ctrl_integrity_check	chip_sw_rom_ctrl_integrity_check	5.473m	9.902ms	1	1	100.00
V2	chip_sw_rstmgr_non_sys_reset_info	chip_sw_pwrmgr_all_reset_reqs	19.613m	11.119ms	1	1	100.00
		chip_sw_pwrmgr_random_sleep_all_reset_reqs	26.515m	23.132ms	1	1	100.00
		chip_sw_pwrmgr_wdog_reset	6.501m	5.014ms	1	1	100.00
		chip_sw_pwrmgr_smoketest	3.069m	5.614ms	1	1	100.00
V2	chip_sw_rstmgr_sys_reset_info	chip_rv_dm_ndm_reset_req	4.794m	4.468ms	1	1	100.00
V2	chip_sw_rstmgr_cpu_info	chip_sw_rstmgr_cpu_info	3.907m	4.244ms	0	1	0.00
V2	chip_sw_rstmgr_sw_req_reset	chip_sw_rstmgr_sw_req	4.155m	3.506ms	1	1	100.00
V2	chip_sw_rstmgr_alert_info	chip_sw_rstmgr_alert_info	16.808m	12.753ms	1	1	100.00
V2	chip_sw_rstmgr_sw_rst	chip_sw_rstmgr_sw_rst	3.071m	2.627ms	1	1	100.00
V2	chip_sw_rstmgr_escalation_reset	chip_sw_all_escalation_resets	7.186m	6.141ms	1	1	100.00
V2	chip_sw_rstmgr_alert_handler_reset_enables	chip_sw_alert_handler_lpg_reset_toggle	16.727m	8.030ms	1	1	100.00
V2	chip_sw_nmi_irq	chip_sw_rv_core_ibex_nmi_irq	7.402m	4.476ms	1	1	100.00
V2	chip_sw_rv_core_ibex_rnd	chip_sw_rv_core_ibex_rnd	8.225m	4.957ms	1	1	100.00
V2	chip_sw_rv_core_ibex_address_translation	chip_sw_rv_core_ibex_address_translation	3.020m	3.423ms	1	1	100.00
V2	chip_sw_rv_core_ibex_icache_scrambled_access	chip_sw_rv_core_ibex_icache_invalidate	2.557m	2.550ms	1	1	100.00
V2	chip_sw_rv_core_ibex_fault_dump	chip_sw_rstmgr_cpu_info	3.907m	4.244ms	0	1	0.00
V2	chip_sw_rv_core_ibex_double_fault	chip_sw_rstmgr_cpu_info	3.907m	4.244ms	0	1	0.00
V2	chip_jtag_csr_rw	chip_jtag_csr_rw	10.316m	9.521ms	1	1	100.00
V2	chip_jtag_mem_access	chip_jtag_mem_access	16.377m	13.458ms	1	1	100.00
V2	chip_rv_dm_ndm_reset_req	chip_rv_dm_ndm_reset_req	4.794m	4.468ms	1	1	100.00
V2	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	4.492m	4.932ms	1	1	100.00
V2	chip_rv_dm_access_after_wakeup	chip_sw_rv_dm_access_after_wakeup	3.278m	5.682ms	1	1	100.00
V2	chip_sw_rv_dm_jtag_tap_sel	chip_tap_straps_rma	3.903m	4.377ms	1	1	100.00
V2	chip_rv_dm_lc_disabled	chip_rv_dm_lc_disabled	2.827m	8.038ms	1	1	100.00
V2	chip_sw_plic_all_irqs	chip_plic_all_irqs_0	9.462m	5.123ms	1	1	100.00
		chip_plic_all_irqs_10	4.685m	3.654ms	1	1	100.00
		chip_plic_all_irqs_20	6.365m	4.140ms	1	1	100.00
V2	chip_sw_plic_sw_irq	chip_sw_plic_sw_irq	2.734m	2.837ms	1	1	100.00
V2	chip_sw_timer	chip_sw_rv_timer_irq	3.044m	2.703ms	1	1	100.00
V2	chip_sw_spi_device_flash_mode	rom_e2e_smoke	41.330m	15.024ms	1	1	100.00
V2	chip_sw_spi_device_pass_through	chip_sw_spi_device_pass_through	6.556m	6.525ms	1	1	100.00
V2	chip_sw_spi_device_pass_through_collision	chip_sw_spi_device_pass_through_collision	3.082m	3.676ms	0	1	0.00
V2	chip_sw_spi_device_tpm	chip_sw_spi_device_tpm	2.899m	3.231ms	1	1	100.00
V2	chip_sw_spi_host_tx_rx	chip_sw_spi_host_tx_rx	2.554m	2.448ms	1	1	100.00
V2	chip_sw_sram_scrambled_access	chip_sw_sram_ctrl_scrambled_access	5.188m	3.909ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	6.034m	4.373ms	1	1	100.00
V2	chip_sw_sleep_sram_ret_contents	chip_sw_sleep_sram_ret_contents_no_scramble	7.171m	6.846ms	1	1	100.00
		chip_sw_sleep_sram_ret_contents_scramble	7.847m	8.131ms	1	1	100.00
V2	chip_sw_sram_execution	chip_sw_sram_ctrl_execution_main	9.690m	8.746ms	1	1	100.00
V2	chip_sw_sram_lc_escalation	chip_sw_all_escalation_resets	7.186m	6.141ms	1	1	100.00
		chip_sw_data_integrity_escalation	7.672m	4.839ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_reset	chip_sw_pwrmgr_sysrst_ctrl_reset	10.187m	6.697ms	1	1	100.00
		chip_sw_sysrst_ctrl_reset	20.447m	23.803ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_inputs	chip_sw_sysrst_ctrl_inputs	2.060m	2.748ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_outputs	chip_sw_sysrst_ctrl_outputs	3.907m	3.573ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_in_irq	chip_sw_sysrst_ctrl_in_irq	5.580m	3.978ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_sleep_wakeup	chip_sw_sysrst_ctrl_reset	20.447m	23.803ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_sleep_reset	chip_sw_sysrst_ctrl_reset	20.447m	23.803ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_ec_rst_l	chip_sw_sysrst_ctrl_ec_rst_l	43.303m	20.934ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_flash_wp_l	chip_sw_sysrst_ctrl_ec_rst_l	43.303m	20.934ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_ulp_z3_wakeup	chip_sw_sysrst_ctrl_ulp_z3_wakeup	4.081m	4.464ms	1	1	100.00
		chip_sw_adc_ctrl_sleep_debug_cable_wakeup	50.809m	34.359ms	0	1	0.00
V2	chip_sw_usbdev_vbus	chip_sw_usbdev_vbus	1.997m	2.441ms	1	1	100.00
V2	chip_sw_usbdev_pullup	chip_sw_usbdev_pullup	2.450m	2.755ms	1	1	100.00
V2	chip_sw_usbdev_aon_pullup	chip_sw_usbdev_aon_pullup	4.307m	3.489ms	1	1	100.00
V2	chip_sw_usbdev_setup_rx	chip_sw_usbdev_setuprx	4.936m	4.067ms	1	1	100.00
V2	chip_sw_usbdev_config_host	chip_sw_usbdev_config_host	16.562m	8.034ms	1	1	100.00
V2	chip_sw_usbdev_pincfg	chip_sw_usbdev_pincfg	1.396h	31.967ms	1	1	100.00
V2	chip_sw_usbdev_tx_rx	chip_sw_usbdev_dpi	30.422m	12.226ms	1	1	100.00
V2	chip_sw_usbdev_toggle_restore	chip_sw_usbdev_toggle_restore	2.196m	2.704ms	1	1	100.00
V2		TOTAL			239	275	86.91
V2S	chip_sw_aes_masking_off	chip_sw_aes_masking_off	2.831m	3.155ms	1	1	100.00
V2S	chip_sw_rv_core_ibex_lockstep_glitch	chip_sw_rv_core_ibex_lockstep_glitch	1.641m	3.073ms	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	chip_sw_coremark	chip_sw_coremark	2.585h	72.146ms	1	1	100.00
V3	chip_sw_power_max_load	chip_sw_power_virus	6.943m	3.829ms	0	1	0.00
V3	rom_e2e_debug	rom_e2e_jtag_debug_test_unlocked0	18.444m	10.438ms	1	1	100.00
		rom_e2e_jtag_debug_dev	20.608m	12.172ms	1	1	100.00
		rom_e2e_jtag_debug_rma	19.123m	11.841ms	1	1	100.00
V3	rom_e2e_jtag_inject	rom_e2e_jtag_inject_test_unlocked0	2.752m	3.413ms	1	1	100.00
		rom_e2e_jtag_inject_dev	4.642m	5.959ms	1	1	100.00
		rom_e2e_jtag_inject_rma	3.271m	5.940ms	1	1	100.00
V3	rom_e2e_self_hash	rom_e2e_self_hash	11.051s		0	1	0.00
V3	chip_sw_clkmgr_jitter_cycle_measurements	chip_sw_clkmgr_jitter_frequency	9.579m	5.040ms	1	1	100.00
V3	chip_sw_edn_boot_mode	chip_sw_edn_boot_mode	4.993m	2.432ms	1	1	100.00
V3	chip_sw_edn_auto_mode	chip_sw_edn_auto_mode	16.354m	6.076ms	1	1	100.00
V3	chip_sw_edn_sw_mode	chip_sw_edn_sw_mode	17.176m	7.806ms	1	1	100.00
V3	chip_sw_edn_kat	chip_sw_edn_kat	3.487m	2.207ms	1	1	100.00
V3	chip_sw_flash_memory_protection	chip_sw_flash_ctrl_mem_protection	9.896m	5.468ms	1	1	100.00
V3	chip_sw_otp_ctrl_vendor_test_csr_access	chip_sw_otp_ctrl_vendor_test_csr_access	2.425m	2.718ms	1	1	100.00
V3	chip_sw_otp_ctrl_escalation	chip_sw_otp_ctrl_escalation	6.720m	5.387ms	1	1	100.00
V3	chip_sw_sensor_ctrl_deep_sleep_wake_up	chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up	3.098m	4.727ms	1	1	100.00
V3	chip_sw_pwrmgr_usb_clk_disabled_when_active	chip_sw_pwrmgr_usb_clk_disabled_when_active	4.642m	4.432ms	1	1	100.00
V3	chip_sw_all_resets	chip_sw_pwrmgr_all_reset_reqs	19.613m	11.119ms	1	1	100.00
V3	chip_rv_dm_perform_debug	rom_e2e_jtag_debug_test_unlocked0	18.444m	10.438ms	1	1	100.00
		rom_e2e_jtag_debug_dev	20.608m	12.172ms	1	1	100.00
		rom_e2e_jtag_debug_rma	19.123m	11.841ms	1	1	100.00
V3	chip_sw_rv_dm_access_after_hw_reset	chip_sw_rv_dm_access_after_escalation_reset	5.910m	5.287ms	1	1	100.00
V3	chip_sw_plic_alerts	chip_sw_all_escalation_resets	7.186m	6.141ms	1	1	100.00
V3	tick_configuration	chip_sw_rv_timer_systick_test	1.572h	38.413ms	1	1	100.00
V3	counter_wrap	chip_sw_rv_timer_systick_test	1.572h	38.413ms	1	1	100.00
V3	chip_sw_spi_device_output_when_disabled_or_sleeping	chip_sw_spi_device_pinmux_sleep_retention	2.595m	3.227ms	1	1	100.00
V3	chip_sw_uart_watermarks	chip_sw_uart_tx_rx	5.583m	4.786ms	1	1	100.00
V3	chip_sw_usbdev_stream	chip_sw_usbdev_stream	54.247m	18.497ms	1	1	100.00
V3		TOTAL			21	23	91.30
	Unmapped tests	chip_sival_flash_info_access	2.476m	3.009ms	1	1	100.00
		chip_sw_rstmgr_rst_cnsty_escalation	5.611m	4.394ms	1	1	100.00
		chip_sw_otp_ctrl_rot_auth_config	37.603m	25.742ms	0	1	0.00
		chip_sw_otp_ctrl_ecc_error_vendor_test	2.942m	3.116ms	1	1	100.00
		chip_sw_otp_ctrl_descrambling	3.051m	3.094ms	1	1	100.00
		chip_sw_pwrmgr_lowpower_cancel	3.903m	3.561ms	1	1	100.00
		chip_sw_pwrmgr_sleep_wake_5_bug	10.455s		0	1	0.00
		chip_sw_flash_ctrl_write_clear	3.099m	2.892ms	1	1	100.00
		TOTAL			285	326	87.42

Failure Buckets

UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_*.signed.*.scr.vmem could not be opened for r mode has 11 failures:
- Test rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0 has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0.48782949363588230600719117717260594445479527400590286089128087899934763954195
    Line 511, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0/latest/run.log
```
  UVM_FATAL @  10.220001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.220001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_bad_b_good_dev has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_bad_b_good_dev.64485468240162442697169816838518987262044620438319342293960459199688362179160
    Line 522, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_dev/latest/run.log
```
  UVM_FATAL @  10.240001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.240001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_bad_b_good_prod has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_bad_b_good_prod.104963080952231813675313479329089970668206214683903752535877890766850705688679
    Line 496, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod/latest/run.log
```
  UVM_FATAL @  10.380001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.380001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_bad_b_good_prod_end has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_bad_b_good_prod_end.23768148818434277494629211066860396515841854162114401792973150513877359867583
    Line 515, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod_end/latest/run.log
```
  UVM_FATAL @  10.400001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.400001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_bad_b_good_rma has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_bad_b_good_rma.48107414214078599670816345292640349907546949702160682754950816489457628706695
    Line 529, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_rma/latest/run.log
```
  UVM_FATAL @  10.340001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.340001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- ... and 6 more tests.
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_*.signed.*.scr.vmem could not be opened for r mode has 5 failures:
- Test rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0 has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0.3018597727410031858807736941412539902039146605635960513134903407305242548971
    Line 498, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0/latest/run.log
```
  UVM_FATAL @  10.180001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.180001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_good_b_bad_dev has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_good_b_bad_dev.70020932517469895583752259274506255131661089168765190630309718349573413183868
    Line 500, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_dev/latest/run.log
```
  UVM_FATAL @  10.280001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.280001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_good_b_bad_prod has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_good_b_bad_prod.15573348463076101712219092210367077967524310341072565127603985800792956037481
    Line 510, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod/latest/run.log
```
  UVM_FATAL @  10.360001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.360001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_good_b_bad_prod_end has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_good_b_bad_prod_end.19853484247195059792892559060684412896899027677290834146203006516664982076576
    Line 488, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod_end/latest/run.log
```
  UVM_FATAL @  10.360001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.360001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_good_b_bad_rma has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_good_b_bad_rma.109122690586203957372228675870856785444568139545001270989962962048873456738263
    Line 478, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_rma/latest/run.log
```
  UVM_FATAL @  10.240001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.240001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_*.signed.*.scr.vmem could not be opened for r mode has 3 failures:
- Test rom_e2e_sigverify_always_a_nothing_b_bad_prod has 1 failures.
  - 0.rom_e2e_sigverify_always_a_nothing_b_bad_prod.96215638047637588921704768086733028570491847364006014327002945623742471901928
    Line 492, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod/latest/run.log
```
  UVM_FATAL @  10.320001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.320001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_sigverify_always_a_nothing_b_bad_prod_end has 1 failures.
  - 0.rom_e2e_sigverify_always_a_nothing_b_bad_prod_end.41367749186215241949622387029375285376144711262725118514299659606422178218610
    Line 504, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod_end/latest/run.log
```
  UVM_FATAL @  10.100001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.100001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_sigverify_always_a_nothing_b_bad_rma has 1 failures.
  - 0.rom_e2e_sigverify_always_a_nothing_b_bad_rma.86047273496305711800852282501134536348270975187050047281115563812085560618100
    Line 467, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_rma/latest/run.log
```
  UVM_FATAL @  10.240001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.240001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

Job returned non-zero exit code has 2 failures:

Test chip_sw_pwrmgr_sleep_wake_5_bug has 1 failures.

0.chip_sw_pwrmgr_sleep_wake_5_bug.5515458132155970557936704925289668290885957971113929661550164543019650964198
Log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_pwrmgr_sleep_wake_5_bug/latest/run.log

  Computing main repo mapping:
  Loading:
  Loading: 0 packages loaded
  WARNING: Target pattern parsing failed.
  ERROR: Skipping '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD
  ERROR: no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD
  INFO: Elapsed time: 0.154s
  INFO: 0 processes.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

Test rom_e2e_self_hash has 1 failures.

0.rom_e2e_self_hash.103359823225106401139167758878976061900631328792013157721147052382691742168490
Log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_self_hash/latest/run.log

  Computing main repo mapping:
  Loading:
  Loading: 0 packages loaded
  WARNING: Target pattern parsing failed.
  ERROR: Skipping '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD
  ERROR: no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD
  INFO: Elapsed time: 0.454s
  INFO: 0 processes.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_test_key_*.signed.*.scr.vmem could not be opened for r mode has 2 failures:
- Test rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0 has 1 failures.
  - 0.rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0.28076201255453781275089084239997429781121799981087719728861829747859563288339
    Line 546, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0/latest/run.log
```
  UVM_FATAL @  10.220001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_test_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.220001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0 has 1 failures.
  - 0.rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0.40962196911207138385635998927778505105407976200179828529851032512120437177610
    Line 460, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0/latest/run.log
```
  UVM_FATAL @  10.260001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_test_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.260001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_dev_key_*.signed.*.scr.vmem could not be opened for r mode has 2 failures:
- Test rom_e2e_sigverify_always_a_bad_b_bad_dev has 1 failures.
  - 0.rom_e2e_sigverify_always_a_bad_b_bad_dev.97192352193704451664198327163808583670999868027076867624860666023094786680797
    Line 529, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_bad_dev/latest/run.log
```
  UVM_FATAL @  10.120001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_dev_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.120001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_sigverify_always_a_bad_b_nothing_dev has 1 failures.
  - 0.rom_e2e_sigverify_always_a_bad_b_nothing_dev.45204612290573498867532134689832907176519373710507857618403150624769792505839
    Line 554, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_nothing_dev/latest/run.log
```
  UVM_FATAL @  10.140001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_dev_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.140001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Offending '(!$isunknown(pin_wkup_req_o))' has 1 failures:
- Test chip_sw_sleep_pin_wake has 1 failures.
  - 0.chip_sw_sleep_pin_wake.11181762360307607284878732359975158461231879330902317276571701686074798384267
    Line 459, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_sleep_pin_wake/latest/run.log
```
      Offending '(!$isunknown(pin_wkup_req_o))'
  UVM_ERROR @ 2354.299000 us: (pinmux.sv:662) [ASSERT FAILED] AonWkupReqKnownO_A
  UVM_INFO @ 2354.299000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:379)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty has 1 failures:
- Test chip_sw_spi_device_pass_through_collision has 1 failures.
  - 0.chip_sw_spi_device_pass_through_collision.73658607072178000508097186484410880907696234558719617164313786461376581923321
    Line 407, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_spi_device_pass_through_collision/latest/run.log
```
  UVM_ERROR @ 3676.408905 us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:379)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty
  UVM_INFO @ 3676.408905 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [otp_ctrl_rot_auth_config_test_sim_dv(sw/device/tests/otp_ctrl_rot_auth_config_test.c:22)] CHECK-STATUS-fail: @@@:* = ErrorError has 1 failures:
- Test chip_sw_otp_ctrl_rot_auth_config has 1 failures.
  - 0.chip_sw_otp_ctrl_rot_auth_config.17965474887995447001250424957511709272663946821465303867660940578439811878746
    Line 447, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_otp_ctrl_rot_auth_config/latest/run.log
```
  UVM_ERROR @ 25741.848469 us: (sw_logger_if.sv:526) [otp_ctrl_rot_auth_config_test_sim_dv(sw/device/tests/otp_ctrl_rot_auth_config_test.c:22)] CHECK-STATUS-fail: @@@:0 = ErrorError
  UVM_INFO @ 25741.848469 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@87780) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_sw_rstmgr_cpu_info has 1 failures.

0.chip_sw_rstmgr_cpu_info.32029691234812128348863334355107129182363650564545212360872100972269041960360
Line 420, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_rstmgr_cpu_info/latest/run.log

  UVM_ERROR @ 4244.456268 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (1 [0x1] vs 0 [0x0]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@87780) { a_addr: 'h8  a_data: 'h0  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h0  a_opcode: 'h0  a_user: 'h259aa  d_param: 'h0  d_source: 'h0  d_data: 'h0  d_size: 'h2  d_opcode: 'h0  d_error: 'h1  d_sink: 'h0  d_user: 'h1f2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 4244.456268 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (chip_sw_base_vseq.sv:317) virtual_sequencer [chip_sw_adc_ctrl_sleep_debug_cable_wakeup_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = * ns has 1 failures:
- Test chip_sw_adc_ctrl_sleep_debug_cable_wakeup has 1 failures.
  - 0.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.7371507955010538284627033663715862848704113418305772081001841536167145147331
    Line 414, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_adc_ctrl_sleep_debug_cable_wakeup/latest/run.log
```
  UVM_ERROR @ 34358.537166 us: (chip_sw_base_vseq.sv:317) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_adc_ctrl_sleep_debug_cable_wakeup_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = 18000000 ns

  UVM_INFO @ 34358.537166 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_test_sim_dv(hw/top_earlgrey/sw/autogen/tests/alert_test.c:307)] CHECK-fail: Expect alert *! has 1 failures:
- Test chip_sw_alert_test has 1 failures.
  - 0.chip_sw_alert_test.35778042523184146547387822629077146186129064360235171407092620708658805219487
    Line 390, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_alert_test/latest/run.log
```
  UVM_ERROR @ 3009.488936 us: (sw_logger_if.sv:526) [alert_test_sim_dv(hw/top_earlgrey/sw/autogen/tests/alert_test.c:307)] CHECK-fail: Expect alert 42!
  UVM_INFO @ 3009.488936 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0) has 1 failures:
- Test chip_sw_alert_handler_lpg_sleep_mode_alerts has 1 failures.
  - 0.chip_sw_alert_handler_lpg_sleep_mode_alerts.40765739100008119297791410356094008103929049817654831080193306710989001492086
    Line 396, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log
```
  UVM_ERROR @ 2544.910320 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
  UVM_INFO @ 2544.910320 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Job timed out after * minutes has 1 failures:
- Test chip_sw_alert_handler_lpg_sleep_mode_pings has 1 failures.
  - 0.chip_sw_alert_handler_lpg_sleep_mode_pings.66130545064642497419604092213990756454809148943329338288869280310709757604466
    Log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_alert_handler_lpg_sleep_mode_pings/latest/run.log
```
  Job timed out after 240 minutes
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [hmac_functest_sim_dv(sw/device/tests/crypto/hmac_functest.c:79)] Finished test run_test_vector: *. has 1 failures:
- Test chip_sw_hmac_oneshot has 1 failures.
  - 0.chip_sw_hmac_oneshot.74292652503425158816352534044637762861670451968840744683617433402229480694941
    Line 395, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_hmac_oneshot/latest/run.log
```
  UVM_ERROR @ 2684.369108 us: (sw_logger_if.sv:526) [hmac_functest_sim_dv(sw/device/tests/crypto/hmac_functest.c:79)] Finished test run_test_vector: 8000534a.
  UVM_INFO @ 2684.369108 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@35344) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_tl_errors has 1 failures.

0.chip_tl_errors.14959046076713187209512357762155741935952707417338917436758682003902544833041
Line 214, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_tl_errors/latest/run.log

  UVM_ERROR @ 2262.515440 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@35344) { a_addr: 'h106b4  a_data: 'h5a180e02  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h14  a_opcode: 'h4  a_user: 'h19ecf  d_param: 'h0  d_source: 'h14  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 2262.515440 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (chip_sw_power_idle_load_vseq.sv:91) virtual_sequencer [chip_sw_power_idle_load_vseq] PWMCH* : pkt* Clock period is wrong. rcv : * exp : * has 1 failures:
- Test chip_sw_power_idle_load has 1 failures.
  - 0.chip_sw_power_idle_load.21086915518222125519391810258754686115902997356577008691232977136595133099468
    Line 397, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_power_idle_load/latest/run.log
```
  UVM_ERROR @ 3134.482500 us: (chip_sw_power_idle_load_vseq.sv:91) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_power_idle_load_vseq] PWMCH5 : pkt3 Clock period is wrong.  rcv : 2  exp : 32
  UVM_INFO @ 3134.482500 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (chip_sw_power_sleep_load_vseq.sv:114) virtual_sequencer [chip_sw_power_sleep_load_vseq] PWMCH* : pkt* Clock period is wrong. rcv : * exp : * has 1 failures:
- Test chip_sw_power_sleep_load has 1 failures.
  - 0.chip_sw_power_sleep_load.9645285179266419989269811893969721557184343638337968059832581249093337559622
    Line 407, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_power_sleep_load/latest/run.log
```
  UVM_ERROR @ 3343.990000 us: (chip_sw_power_sleep_load_vseq.sv:114) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_power_sleep_load_vseq] PWMCH5 : pkt3 Clock period is wrong.  rcv : 2  exp : 32
  UVM_INFO @ 3343.990000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (chip_sw_power_virus_vseq.sv:196) [chip_sw_power_virus_vseq] Check failed csrng_acmd_q >= * (* [*] vs * [*]) has 1 failures:
- Test chip_sw_power_virus has 1 failures.
  - 0.chip_sw_power_virus.40888565714841406277966073287537839430342014991936314817355535367636738098824
    Line 444, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_power_virus/latest/run.log
```
  UVM_ERROR @ 3828.894034 us: (chip_sw_power_virus_vseq.sv:196) [uvm_test_top.env.virtual_sequencer.chip_sw_power_virus_vseq] Check failed csrng_acmd_q >= 2 (1 [0x1] vs 2 [0x2])
  UVM_INFO @ 3828.894034 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_test_key_*.signed.*.scr.vmem could not be opened for r mode has 1 failures:
- Test rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0 has 1 failures.
  - 0.rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0.100744349259068199540363744307976303918241207028934092273833526529215883051375
    Line 513, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0/latest/run.log
```
  UVM_FATAL @  10.300001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_test_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.300001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_dev_key_*.signed.*.scr.vmem could not be opened for r mode has 1 failures:
- Test rom_e2e_sigverify_always_a_nothing_b_bad_dev has 1 failures.
  - 0.rom_e2e_sigverify_always_a_nothing_b_bad_dev.51016702471042607832905931976491712692156947181752983703480877914744737682251
    Line 521, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_dev/latest/run.log
```
  UVM_FATAL @  10.200001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_dev_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.200001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@31980) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_csr_mem_rw_with_rand_reset has 1 failures.

0.chip_csr_mem_rw_with_rand_reset.7970219568701517333082651543780639247363024037019156424420142747913189502164
Line 221, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_csr_mem_rw_with_rand_reset/latest/run.log

  UVM_ERROR @ 3069.336286 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@31980) { a_addr: 'h104a0  a_data: 'h94493062  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h3a  a_opcode: 'h4  a_user: 'h1bdd0  d_param: 'h0  d_source: 'h3a  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 3069.336286 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---