ADC_CTRL Simulation Results

Wednesday October 08 2025 17:04:29 UTC

GitHub Revision: e4ce7cf

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	adc_ctrl_smoke	15.930s	5.908ms	1	1	100.00
V1	csr_hw_reset	adc_ctrl_csr_hw_reset	1.880s	1.274ms	1	1	100.00
V1	csr_rw	adc_ctrl_csr_rw	0.860s	445.622us	1	1	100.00
V1	csr_bit_bash	adc_ctrl_csr_bit_bash	9.890s	11.258ms	1	1	100.00
V1	csr_aliasing	adc_ctrl_csr_aliasing	2.100s	702.112us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	adc_ctrl_csr_mem_rw_with_rand_reset	1.450s	566.756us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	adc_ctrl_csr_rw	0.860s	445.622us	1	1	100.00
		adc_ctrl_csr_aliasing	2.100s	702.112us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	filters_polled	adc_ctrl_filters_polled	8.722m	330.549ms	1	1	100.00
V2	filters_polled_fixed	adc_ctrl_filters_polled_fixed	15.610m	491.876ms	1	1	100.00
V2	filters_interrupt	adc_ctrl_filters_interrupt	3.755m	490.539ms	1	1	100.00
V2	filters_interrupt_fixed	adc_ctrl_filters_interrupt_fixed	3.970m	330.039ms	1	1	100.00
V2	filters_wakeup	adc_ctrl_filters_wakeup	1.900m	188.726ms	1	1	100.00
V2	filters_wakeup_fixed	adc_ctrl_filters_wakeup_fixed	14.435m	614.504ms	1	1	100.00
V2	filters_both	adc_ctrl_filters_both	10.810m	365.221ms	1	1	100.00
V2	clock_gating	adc_ctrl_clock_gating	4.154m	167.786ms	1	1	100.00
V2	poweron_counter	adc_ctrl_poweron_counter	7.290s	4.218ms	1	1	100.00
V2	lowpower_counter	adc_ctrl_lowpower_counter	18.280s	43.994ms	1	1	100.00
V2	fsm_reset	adc_ctrl_fsm_reset	2.644m	101.141ms	1	1	100.00
V2	stress_all	adc_ctrl_stress_all	56.470s	31.474ms	1	1	100.00
V2	alert_test	adc_ctrl_alert_test	1.080s	554.186us	1	1	100.00
V2	intr_test	adc_ctrl_intr_test	1.590s	479.216us	1	1	100.00
V2	tl_d_oob_addr_access	adc_ctrl_tl_errors	1.960s	647.734us	1	1	100.00
V2	tl_d_illegal_access	adc_ctrl_tl_errors	1.960s	647.734us	1	1	100.00
V2	tl_d_outstanding_access	adc_ctrl_csr_hw_reset	1.880s	1.274ms	1	1	100.00
		adc_ctrl_csr_rw	0.860s	445.622us	1	1	100.00
		adc_ctrl_csr_aliasing	2.100s	702.112us	1	1	100.00
		adc_ctrl_same_csr_outstanding	12.010s	5.013ms	1	1	100.00
V2	tl_d_partial_access	adc_ctrl_csr_hw_reset	1.880s	1.274ms	1	1	100.00
		adc_ctrl_csr_rw	0.860s	445.622us	1	1	100.00
		adc_ctrl_csr_aliasing	2.100s	702.112us	1	1	100.00
		adc_ctrl_same_csr_outstanding	12.010s	5.013ms	1	1	100.00
V2		TOTAL			16	16	100.00
V2S	tl_intg_err	adc_ctrl_sec_cm	5.320s	8.448ms	1	1	100.00
		adc_ctrl_tl_intg_err	5.040s	8.012ms	1	1	100.00
V2S	sec_cm_bus_integrity	adc_ctrl_tl_intg_err	5.040s	8.012ms	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	stress_all_with_rand_reset	adc_ctrl_stress_all_with_rand_reset	12.860s	77.212ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			25	25	100.00