HMAC Simulation Results

Wednesday October 08 2025 17:04:29 UTC

GitHub Revision: e4ce7cf

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke hmac_smoke 10.490s 2.146ms 1 1 100.00
V1 csr_hw_reset hmac_csr_hw_reset 0.720s 20.357us 1 1 100.00
V1 csr_rw hmac_csr_rw 0.870s 19.573us 1 1 100.00
V1 csr_bit_bash hmac_csr_bit_bash 9.860s 645.618us 1 1 100.00
V1 csr_aliasing hmac_csr_aliasing 4.100s 305.443us 1 1 100.00
V1 csr_mem_rw_with_rand_reset hmac_csr_mem_rw_with_rand_reset 1.580s 23.413us 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr hmac_csr_rw 0.870s 19.573us 1 1 100.00
hmac_csr_aliasing 4.100s 305.443us 1 1 100.00
V1 TOTAL 6 6 100.00
V2 long_msg hmac_long_msg 51.660s 20.703ms 1 1 100.00
V2 back_pressure hmac_back_pressure 7.280s 156.677us 1 1 100.00
V2 test_vectors hmac_test_sha256_vectors 8.020s 971.548us 1 1 100.00
hmac_test_sha384_vectors 6.113m 21.647ms 1 1 100.00
hmac_test_sha512_vectors 6.315m 15.443ms 1 1 100.00
hmac_test_hmac256_vectors 8.640s 578.435us 1 1 100.00
hmac_test_hmac384_vectors 7.090s 333.070us 1 1 100.00
hmac_test_hmac512_vectors 8.430s 1.023ms 1 1 100.00
V2 burst_wr hmac_burst_wr 16.430s 4.875ms 1 1 100.00
V2 datapath_stress hmac_datapath_stress 1.763m 5.172ms 1 1 100.00
V2 error hmac_error 56.260s 11.778ms 1 1 100.00
V2 wipe_secret hmac_wipe_secret 1.190m 8.862ms 1 1 100.00
V2 save_and_restore hmac_smoke 10.490s 2.146ms 1 1 100.00
hmac_long_msg 51.660s 20.703ms 1 1 100.00
hmac_back_pressure 7.280s 156.677us 1 1 100.00
hmac_datapath_stress 1.763m 5.172ms 1 1 100.00
hmac_burst_wr 16.430s 4.875ms 1 1 100.00
hmac_stress_all 19.187m 218.171ms 1 1 100.00
V2 fifo_empty_status_interrupt hmac_smoke 10.490s 2.146ms 1 1 100.00
hmac_long_msg 51.660s 20.703ms 1 1 100.00
hmac_back_pressure 7.280s 156.677us 1 1 100.00
hmac_datapath_stress 1.763m 5.172ms 1 1 100.00
hmac_wipe_secret 1.190m 8.862ms 1 1 100.00
hmac_test_sha256_vectors 8.020s 971.548us 1 1 100.00
hmac_test_sha384_vectors 6.113m 21.647ms 1 1 100.00
hmac_test_sha512_vectors 6.315m 15.443ms 1 1 100.00
hmac_test_hmac256_vectors 8.640s 578.435us 1 1 100.00
hmac_test_hmac384_vectors 7.090s 333.070us 1 1 100.00
hmac_test_hmac512_vectors 8.430s 1.023ms 1 1 100.00
V2 wide_digest_configurable_key_length hmac_smoke 10.490s 2.146ms 1 1 100.00
hmac_long_msg 51.660s 20.703ms 1 1 100.00
hmac_back_pressure 7.280s 156.677us 1 1 100.00
hmac_datapath_stress 1.763m 5.172ms 1 1 100.00
hmac_burst_wr 16.430s 4.875ms 1 1 100.00
hmac_error 56.260s 11.778ms 1 1 100.00
hmac_wipe_secret 1.190m 8.862ms 1 1 100.00
hmac_test_sha256_vectors 8.020s 971.548us 1 1 100.00
hmac_test_sha384_vectors 6.113m 21.647ms 1 1 100.00
hmac_test_sha512_vectors 6.315m 15.443ms 1 1 100.00
hmac_test_hmac256_vectors 8.640s 578.435us 1 1 100.00
hmac_test_hmac384_vectors 7.090s 333.070us 1 1 100.00
hmac_test_hmac512_vectors 8.430s 1.023ms 1 1 100.00
hmac_stress_all 19.187m 218.171ms 1 1 100.00
V2 stress_all hmac_stress_all 19.187m 218.171ms 1 1 100.00
V2 alert_test hmac_alert_test 0.580s 23.068us 1 1 100.00
V2 intr_test hmac_intr_test 0.660s 11.405us 1 1 100.00
V2 tl_d_oob_addr_access hmac_tl_errors 2.220s 126.541us 1 1 100.00
V2 tl_d_illegal_access hmac_tl_errors 2.220s 126.541us 1 1 100.00
V2 tl_d_outstanding_access hmac_csr_hw_reset 0.720s 20.357us 1 1 100.00
hmac_csr_rw 0.870s 19.573us 1 1 100.00
hmac_csr_aliasing 4.100s 305.443us 1 1 100.00
hmac_same_csr_outstanding 1.330s 476.519us 1 1 100.00
V2 tl_d_partial_access hmac_csr_hw_reset 0.720s 20.357us 1 1 100.00
hmac_csr_rw 0.870s 19.573us 1 1 100.00
hmac_csr_aliasing 4.100s 305.443us 1 1 100.00
hmac_same_csr_outstanding 1.330s 476.519us 1 1 100.00
V2 TOTAL 17 17 100.00
V2S tl_intg_err hmac_sec_cm 1.130s 912.076us 1 1 100.00
hmac_tl_intg_err 2.970s 289.006us 1 1 100.00
V2S sec_cm_bus_integrity hmac_tl_intg_err 2.970s 289.006us 1 1 100.00
V2S TOTAL 2 2 100.00
V3 write_config_and_secret_key_during_msg_wr hmac_smoke 10.490s 2.146ms 1 1 100.00
V3 stress_reset hmac_stress_reset 2.650s 664.453us 1 1 100.00
V3 stress_all_with_rand_reset hmac_stress_all_with_rand_reset 1.392m 23.128ms 1 1 100.00
V3 TOTAL 2 2 100.00
Unmapped tests hmac_directed 1.110s 24.347us 1 1 100.00
TOTAL 28 28 100.00