I2C Simulation Results

Wednesday October 08 2025 17:04:29 UTC

GitHub Revision: e4ce7cf

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	host_smoke	i2c_host_smoke	54.720s	3.379ms	1	1	100.00
V1	target_smoke	i2c_target_smoke	21.000s	1.683ms	1	1	100.00
V1	csr_hw_reset	i2c_csr_hw_reset	0.890s	30.727us	1	1	100.00
V1	csr_rw	i2c_csr_rw	0.670s	43.967us	1	1	100.00
V1	csr_bit_bash	i2c_csr_bit_bash	3.450s	228.397us	1	1	100.00
V1	csr_aliasing	i2c_csr_aliasing	1.130s	116.930us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	i2c_csr_mem_rw_with_rand_reset	1.230s	49.935us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	i2c_csr_rw	0.670s	43.967us	1	1	100.00
		i2c_csr_aliasing	1.130s	116.930us	1	1	100.00
V1		TOTAL			7	7	100.00
V2	host_error_intr	i2c_host_error_intr	0.970s	49.755us	0	1	0.00
V2	host_stress_all	i2c_host_stress_all	4.012m	10.693ms	0	1	0.00
V2	host_maxperf	i2c_host_perf	6.248m	26.890ms	1	1	100.00
V2	host_override	i2c_host_override	0.910s	77.299us	1	1	100.00
V2	host_fifo_watermark	i2c_host_fifo_watermark	44.620s	2.796ms	1	1	100.00
V2	host_fifo_overflow	i2c_host_fifo_overflow	43.840s	10.994ms	1	1	100.00
V2	host_fifo_reset	i2c_host_fifo_reset_fmt	1.100s	168.749us	1	1	100.00
		i2c_host_fifo_fmt_empty	3.390s	2.073ms	1	1	100.00
		i2c_host_fifo_reset_rx	2.010s	389.539us	1	1	100.00
V2	host_fifo_full	i2c_host_fifo_full	1.230m	7.558ms	1	1	100.00
V2	host_timeout	i2c_host_stretch_timeout	12.890s	1.309ms	1	1	100.00
V2	i2c_host_mode_toggle	i2c_host_mode_toggle	1.760s	69.546us	1	1	100.00
V2	target_glitch	i2c_target_glitch	2.880s	573.797us	0	1	0.00
V2	target_stress_all	i2c_target_stress_all	21.030s	6.076ms	1	1	100.00
V2	target_maxperf	i2c_target_perf	5.670s	3.293ms	1	1	100.00
V2	target_fifo_empty	i2c_target_stress_rd	25.800s	1.951ms	1	1	100.00
		i2c_target_intr_smoke	8.260s	2.840ms	1	1	100.00
V2	target_fifo_reset	i2c_target_fifo_reset_acq	1.140s	228.624us	1	1	100.00
		i2c_target_fifo_reset_tx	1.390s	218.810us	1	1	100.00
V2	target_fifo_full	i2c_target_stress_wr	21.940s	14.451ms	1	1	100.00
		i2c_target_stress_rd	25.800s	1.951ms	1	1	100.00
		i2c_target_intr_stress_wr	27.700s	21.290ms	1	1	100.00
V2	target_timeout	i2c_target_timeout	5.810s	27.839ms	1	1	100.00
V2	target_clock_stretch	i2c_target_stretch	13.210s	4.484ms	1	1	100.00
V2	bad_address	i2c_target_bad_addr	3.410s	1.545ms	1	1	100.00
V2	target_mode_glitch	i2c_target_hrst	2.620s	616.611us	1	1	100.00
V2	target_fifo_watermark	i2c_target_fifo_watermarks_acq	2.200s	437.277us	1	1	100.00
		i2c_target_fifo_watermarks_tx	1.370s	178.825us	1	1	100.00
V2	host_mode_config_perf	i2c_host_perf	6.248m	26.890ms	1	1	100.00
		i2c_host_perf_precise	2.280s	1.056ms	1	1	100.00
V2	host_mode_clock_stretching	i2c_host_stretch_timeout	12.890s	1.309ms	1	1	100.00
V2	target_mode_tx_stretch_ctrl	i2c_target_tx_stretch_ctrl	1.610s	98.393us	1	1	100.00
V2	target_mode_nack_generation	i2c_target_nack_acqfull	1.980s	1.004ms	1	1	100.00
		i2c_target_nack_acqfull_addr	1.770s	977.057us	1	1	100.00
		i2c_target_nack_txstretch	1.160s	561.115us	1	1	100.00
V2	host_mode_halt_on_nak	i2c_host_may_nack	2.510s	231.128us	1	1	100.00
V2	target_mode_smbus_maxlen	i2c_target_smbus_maxlen	1.950s	577.989us	1	1	100.00
V2	alert_test	i2c_alert_test	0.800s	27.604us	1	1	100.00
V2	intr_test	i2c_intr_test	0.750s	17.497us	1	1	100.00
V2	tl_d_oob_addr_access	i2c_tl_errors	1.240s	25.723us	1	1	100.00
V2	tl_d_illegal_access	i2c_tl_errors	1.240s	25.723us	1	1	100.00
V2	tl_d_outstanding_access	i2c_csr_hw_reset	0.890s	30.727us	1	1	100.00
		i2c_csr_rw	0.670s	43.967us	1	1	100.00
		i2c_csr_aliasing	1.130s	116.930us	1	1	100.00
		i2c_same_csr_outstanding	0.990s	79.993us	1	1	100.00
V2	tl_d_partial_access	i2c_csr_hw_reset	0.890s	30.727us	1	1	100.00
		i2c_csr_rw	0.670s	43.967us	1	1	100.00
		i2c_csr_aliasing	1.130s	116.930us	1	1	100.00
		i2c_same_csr_outstanding	0.990s	79.993us	1	1	100.00
V2		TOTAL			35	38	92.11
V2S	tl_intg_err	i2c_tl_intg_err	1.440s	207.447us	1	1	100.00
		i2c_sec_cm	0.890s	57.971us	1	1	100.00
V2S	sec_cm_bus_integrity	i2c_tl_intg_err	1.440s	207.447us	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	host_stress_all_with_rand_reset	i2c_host_stress_all_with_rand_reset	7.810s	455.169us	0	1	0.00
V3	target_error_intr	i2c_target_unexp_stop	1.340s	1.028ms	0	1	0.00
V3	target_stress_all_with_rand_reset	i2c_target_stress_all_with_rand_reset	0.870s	10.807us	0	1	0.00
V3		TOTAL			0	3	0.00
		TOTAL			44	50	88.00

Failure Buckets

• UVM_ERROR sequencer [sequencer] Get_next_item called twice without item_done or get in between has 2 failures:

  • Test i2c_host_error_intr has 1 failures.

    • 0.i2c_host_error_intr.7435408946997251808597345361889164902081290251349113596739970223086418416274
      Line 83, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_host_error_intr/latest/run.log

        UVM_ERROR @  49755333 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] Get_next_item called twice without item_done or get in between
        UVM_INFO @  49755333 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test i2c_target_stress_all_with_rand_reset has 1 failures.

    • 0.i2c_target_stress_all_with_rand_reset.39054800012370856551200887145601198308090398414254549651467292740537321765220
      Line 82, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_target_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @  10806842 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] Get_next_item called twice without item_done or get in between
        UVM_INFO @  10806842 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (i2c_scoreboard.sv:716) [scoreboard] controller_mode_rd_obs_fifo item uncompared: has 1 failures:

  • Test i2c_host_stress_all has 1 failures.

    • 0.i2c_host_stress_all.84611761782533652393984813400003328880839228586159615535787898335367411361556
      Line 127, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_host_stress_all/latest/run.log

        UVM_ERROR @ 10693111963 ps: (i2c_scoreboard.sv:716) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared:
        ----------------------------------------------------
        Name            Type                Size  Value
        ----------------------------------------------------
        mon_dut_item    i2c_item            -     @2193063
      

• UVM_ERROR sequencer [sequencer] get_next_item/try_next_item called twice without item_done or get in between has 1 failures:

  • Test i2c_target_glitch has 1 failures.

    • 0.i2c_target_glitch.4252942762842017610531754317490945410137918922099548690592190859175174051360
      Line 81, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_target_glitch/latest/run.log

        UVM_ERROR @ 573797044 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] get_next_item/try_next_item called twice without item_done or get in between
        UVM_INFO @ 573797044 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (i2c_base_vseq.sv:1474) [i2c_target_ack_stop_vseq] Check failed obs_intr_state[intr] == exp_val (* [*] vs * [*]) has 1 failures:

  • Test i2c_target_unexp_stop has 1 failures.

    • 0.i2c_target_unexp_stop.17382842813218634732609722662266452284342706554403679853846502241246374591978
      Line 75, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_target_unexp_stop/latest/run.log

        UVM_ERROR @ 1027762815 ps: (i2c_base_vseq.sv:1474) [uvm_test_top.env.virtual_sequencer.i2c_target_ack_stop_vseq] Check failed obs_intr_state[intr] == exp_val (0 [0x0] vs 1 [0x1])
        UVM_INFO @ 1027762815 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (cip_base_vseq.sv:1229) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:

  • Test i2c_host_stress_all_with_rand_reset has 1 failures.

    • 0.i2c_host_stress_all_with_rand_reset.108416596027592085241681959097677394422093987219252248726377895460831240155497
      Line 84, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_host_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 455169010 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 455169010 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---