PATTGEN Simulation Results

Wednesday October 08 2025 17:04:29 UTC

GitHub Revision: `e4ce7cf`

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	pattgen_smoke	2.000s	45.613us	1	1	100.00
V1	csr_hw_reset	pattgen_csr_hw_reset	2.000s	25.335us	1	1	100.00
V1	csr_rw	pattgen_csr_rw	1.000s	49.213us	1	1	100.00
V1	csr_bit_bash	pattgen_csr_bit_bash	2.000s	155.470us	1	1	100.00
V1	csr_aliasing	pattgen_csr_aliasing	1.000s	35.227us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	pattgen_csr_mem_rw_with_rand_reset	1.000s	95.212us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	pattgen_csr_rw	1.000s	49.213us	1	1	100.00
		pattgen_csr_aliasing	1.000s	35.227us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	perf	pattgen_perf	17.250m	600.000ms	0	1	0.00
V2	cnt_rollover	cnt_rollover	11.000s	5.274ms	1	1	100.00
V2	error	pattgen_error	2.000s	17.263us	1	1	100.00
V2	stress_all	pattgen_stress_all	1.100m	10.223ms	0	1	0.00
V2	alert_test	pattgen_alert_test	1.000s	44.129us	1	1	100.00
V2	intr_test	pattgen_intr_test	2.000s	14.009us	1	1	100.00
V2	tl_d_oob_addr_access	pattgen_tl_errors	2.000s	195.836us	1	1	100.00
V2	tl_d_illegal_access	pattgen_tl_errors	2.000s	195.836us	1	1	100.00
V2	tl_d_outstanding_access	pattgen_csr_hw_reset	2.000s	25.335us	1	1	100.00
		pattgen_csr_rw	1.000s	49.213us	1	1	100.00
		pattgen_csr_aliasing	1.000s	35.227us	1	1	100.00
		pattgen_same_csr_outstanding	2.000s	64.190us	1	1	100.00
V2	tl_d_partial_access	pattgen_csr_hw_reset	2.000s	25.335us	1	1	100.00
		pattgen_csr_rw	1.000s	49.213us	1	1	100.00
		pattgen_csr_aliasing	1.000s	35.227us	1	1	100.00
		pattgen_same_csr_outstanding	2.000s	64.190us	1	1	100.00
V2		TOTAL			6	8	75.00
V2S	tl_intg_err	pattgen_tl_intg_err	1.000s	51.856us	1	1	100.00
		pattgen_sec_cm	1.000s	66.158us	1	1	100.00
V2S	sec_cm_bus_integrity	pattgen_tl_intg_err	1.000s	51.856us	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	stress_all_with_rand_reset	pattgen_stress_all_with_rand_reset	17.000s	7.540ms	0	1	0.00
V3		TOTAL			0	1	0.00
	Unmapped tests	pattgen_inactive_level	1.000s	50.540us	1	1	100.00
		TOTAL			15	18	83.33

Failure Buckets

UVM_FATAL (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
- Test pattgen_perf has 1 failures.
  - 0.pattgen_perf.64215508439631637327839679505463904630013992631400874954263758667481934811527
    Line 96, in log /nightly/current_run/scratch/master/pattgen-sim-xcelium/0.pattgen_perf/latest/run.log
```
  UVM_FATAL @ 600000000000 ps: (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of 600000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR (cip_base_vseq.sv:1230) [pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:

Test pattgen_stress_all_with_rand_reset has 1 failures.

0.pattgen_stress_all_with_rand_reset.104777572619395302759582086312647461386353818606171766839199068384330600759402
Line 158, in log /nightly/current_run/scratch/master/pattgen-sim-xcelium/0.pattgen_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 4959175686 ps: (cip_base_vseq.sv:1230) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_ERROR @ 4959195781 ps: (cip_base_vseq.sv:1143) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 4959195781 ps: (cip_base_vseq.sv:1146) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
  Issuing reset for run 2/5
  UVM_INFO @ 4959477031 ps: (cip_base_vseq.sv:1167) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]

UVM_ERROR (pattgen_scoreboard.sv:76) [scoreboard] exp_item_q[i] item uncompared: has 1 failures:
- Test pattgen_stress_all has 1 failures.
  - 0.pattgen_stress_all.113219071890880783823795374827006729791034031632985683491898437937727027504290
    Line 122, in log /nightly/current_run/scratch/master/pattgen-sim-xcelium/0.pattgen_stress_all/latest/run.log
```
  UVM_ERROR @ 10223013723 ps: (pattgen_scoreboard.sv:76) [uvm_test_top.env.scoreboard] exp_item_q[i] item uncompared:
  ------------------------------------
  Name      Type          Size  Value
  ------------------------------------
  exp_item  pattgen_item  -     @10197
```