ROM_CTRL/64KB Simulation Results

Wednesday October 08 2025 17:04:29 UTC

GitHub Revision: e4ce7cf

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke rom_ctrl_smoke 7.930s 1.104ms 1 1 100.00
V1 csr_hw_reset rom_ctrl_csr_hw_reset 11.300s 4.239ms 1 1 100.00
V1 csr_rw rom_ctrl_csr_rw 8.220s 291.704us 1 1 100.00
V1 csr_bit_bash rom_ctrl_csr_bit_bash 9.780s 315.729us 1 1 100.00
V1 csr_aliasing rom_ctrl_csr_aliasing 8.310s 1.073ms 1 1 100.00
V1 csr_mem_rw_with_rand_reset rom_ctrl_csr_mem_rw_with_rand_reset 6.060s 393.898us 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr rom_ctrl_csr_rw 8.220s 291.704us 1 1 100.00
rom_ctrl_csr_aliasing 8.310s 1.073ms 1 1 100.00
V1 mem_walk rom_ctrl_mem_walk 7.470s 385.118us 1 1 100.00
V1 mem_partial_access rom_ctrl_mem_partial_access 10.250s 2.016ms 1 1 100.00
V1 TOTAL 8 8 100.00
V2 max_throughput_chk rom_ctrl_max_throughput_chk 9.450s 304.328us 1 1 100.00
V2 stress_all rom_ctrl_stress_all 27.020s 4.840ms 1 1 100.00
V2 kmac_err_chk rom_ctrl_kmac_err_chk 17.190s 548.133us 1 1 100.00
V2 alert_test rom_ctrl_alert_test 7.980s 1.026ms 1 1 100.00
V2 tl_d_oob_addr_access rom_ctrl_tl_errors 9.240s 2.390ms 1 1 100.00
V2 tl_d_illegal_access rom_ctrl_tl_errors 9.240s 2.390ms 1 1 100.00
V2 tl_d_outstanding_access rom_ctrl_csr_hw_reset 11.300s 4.239ms 1 1 100.00
rom_ctrl_csr_rw 8.220s 291.704us 1 1 100.00
rom_ctrl_csr_aliasing 8.310s 1.073ms 1 1 100.00
rom_ctrl_same_csr_outstanding 6.940s 1.487ms 1 1 100.00
V2 tl_d_partial_access rom_ctrl_csr_hw_reset 11.300s 4.239ms 1 1 100.00
rom_ctrl_csr_rw 8.220s 291.704us 1 1 100.00
rom_ctrl_csr_aliasing 8.310s 1.073ms 1 1 100.00
rom_ctrl_same_csr_outstanding 6.940s 1.487ms 1 1 100.00
V2 TOTAL 6 6 100.00
V2S corrupt_sig_fatal_chk rom_ctrl_corrupt_sig_fatal_chk 1.719m 7.169ms 1 1 100.00
V2S passthru_mem_tl_intg_err rom_ctrl_passthru_mem_tl_intg_err 27.780s 16.804ms 1 1 100.00
V2S tl_intg_err rom_ctrl_sec_cm 7.669m 5.214ms 1 1 100.00
rom_ctrl_tl_intg_err 1.679m 544.148us 1 1 100.00
V2S prim_fsm_check rom_ctrl_sec_cm 7.669m 5.214ms 1 1 100.00
V2S prim_count_check rom_ctrl_sec_cm 7.669m 5.214ms 1 1 100.00
V2S sec_cm_checker_ctr_consistency rom_ctrl_corrupt_sig_fatal_chk 1.719m 7.169ms 1 1 100.00
V2S sec_cm_checker_ctrl_flow_consistency rom_ctrl_corrupt_sig_fatal_chk 1.719m 7.169ms 1 1 100.00
V2S sec_cm_checker_fsm_local_esc rom_ctrl_corrupt_sig_fatal_chk 1.719m 7.169ms 1 1 100.00
V2S sec_cm_compare_ctrl_flow_consistency rom_ctrl_corrupt_sig_fatal_chk 1.719m 7.169ms 1 1 100.00
V2S sec_cm_compare_ctr_consistency rom_ctrl_corrupt_sig_fatal_chk 1.719m 7.169ms 1 1 100.00
V2S sec_cm_compare_ctr_redun rom_ctrl_sec_cm 7.669m 5.214ms 1 1 100.00
V2S sec_cm_fsm_sparse rom_ctrl_sec_cm 7.669m 5.214ms 1 1 100.00
V2S sec_cm_mem_scramble rom_ctrl_smoke 7.930s 1.104ms 1 1 100.00
V2S sec_cm_mem_digest rom_ctrl_smoke 7.930s 1.104ms 1 1 100.00
V2S sec_cm_intersig_mubi rom_ctrl_smoke 7.930s 1.104ms 1 1 100.00
V2S sec_cm_bus_integrity rom_ctrl_tl_intg_err 1.679m 544.148us 1 1 100.00
V2S sec_cm_bus_local_esc rom_ctrl_corrupt_sig_fatal_chk 1.719m 7.169ms 1 1 100.00
rom_ctrl_kmac_err_chk 17.190s 548.133us 1 1 100.00
V2S sec_cm_mux_mubi rom_ctrl_corrupt_sig_fatal_chk 1.719m 7.169ms 1 1 100.00
V2S sec_cm_mux_consistency rom_ctrl_corrupt_sig_fatal_chk 1.719m 7.169ms 1 1 100.00
V2S sec_cm_ctrl_redun rom_ctrl_corrupt_sig_fatal_chk 1.719m 7.169ms 1 1 100.00
V2S sec_cm_ctrl_mem_integrity rom_ctrl_passthru_mem_tl_intg_err 27.780s 16.804ms 1 1 100.00
V2S sec_cm_tlul_fifo_ctr_redun rom_ctrl_sec_cm 7.669m 5.214ms 1 1 100.00
V2S TOTAL 4 4 100.00
V3 stress_all_with_rand_reset rom_ctrl_stress_all_with_rand_reset 1.311m 1.882ms 1 1 100.00
V3 TOTAL 1 1 100.00
TOTAL 19 19 100.00