e4ce7cf| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | random | rv_timer_random | 1.420s | 232.499us | 1 | 1 | 100.00 |
| V1 | csr_hw_reset | rv_timer_csr_hw_reset | 0.760s | 16.918us | 1 | 1 | 100.00 |
| V1 | csr_rw | rv_timer_csr_rw | 0.730s | 35.124us | 1 | 1 | 100.00 |
| V1 | csr_bit_bash | rv_timer_csr_bit_bash | 2.930s | 1.653ms | 1 | 1 | 100.00 |
| V1 | csr_aliasing | rv_timer_csr_aliasing | 0.870s | 50.181us | 1 | 1 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | rv_timer_csr_mem_rw_with_rand_reset | 0.920s | 60.000us | 1 | 1 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | rv_timer_csr_rw | 0.730s | 35.124us | 1 | 1 | 100.00 |
| rv_timer_csr_aliasing | 0.870s | 50.181us | 1 | 1 | 100.00 | ||
| V1 | TOTAL | 6 | 6 | 100.00 | |||
| V2 | random_reset | rv_timer_random_reset | 12.870s | 44.042ms | 0 | 1 | 0.00 |
| V2 | disabled | rv_timer_disabled | 1.000s | 84.000us | 1 | 1 | 100.00 |
| V2 | cfg_update_on_fly | rv_timer_cfg_update_on_fly | 1.111m | 102.975ms | 1 | 1 | 100.00 |
| V2 | no_interrupt_test | rv_timer_cfg_update_on_fly | 1.111m | 102.975ms | 1 | 1 | 100.00 |
| V2 | stress | rv_timer_stress_all | 4.130s | 7.304ms | 1 | 1 | 100.00 |
| V2 | alert_test | rv_timer_alert_test | 0.610s | 41.003us | 1 | 1 | 100.00 |
| V2 | intr_test | rv_timer_intr_test | 0.810s | 46.798us | 1 | 1 | 100.00 |
| V2 | tl_d_oob_addr_access | rv_timer_tl_errors | 2.510s | 61.248us | 1 | 1 | 100.00 |
| V2 | tl_d_illegal_access | rv_timer_tl_errors | 2.510s | 61.248us | 1 | 1 | 100.00 |
| V2 | tl_d_outstanding_access | rv_timer_csr_hw_reset | 0.760s | 16.918us | 1 | 1 | 100.00 |
| rv_timer_csr_rw | 0.730s | 35.124us | 1 | 1 | 100.00 | ||
| rv_timer_csr_aliasing | 0.870s | 50.181us | 1 | 1 | 100.00 | ||
| rv_timer_same_csr_outstanding | 0.890s | 18.457us | 1 | 1 | 100.00 | ||
| V2 | tl_d_partial_access | rv_timer_csr_hw_reset | 0.760s | 16.918us | 1 | 1 | 100.00 |
| rv_timer_csr_rw | 0.730s | 35.124us | 1 | 1 | 100.00 | ||
| rv_timer_csr_aliasing | 0.870s | 50.181us | 1 | 1 | 100.00 | ||
| rv_timer_same_csr_outstanding | 0.890s | 18.457us | 1 | 1 | 100.00 | ||
| V2 | TOTAL | 7 | 8 | 87.50 | |||
| V2S | tl_intg_err | rv_timer_sec_cm | 1.220s | 147.388us | 1 | 1 | 100.00 |
| rv_timer_tl_intg_err | 1.340s | 133.592us | 1 | 1 | 100.00 | ||
| V2S | sec_cm_bus_integrity | rv_timer_tl_intg_err | 1.340s | 133.592us | 1 | 1 | 100.00 |
| V2S | TOTAL | 2 | 2 | 100.00 | |||
| V3 | min_value | rv_timer_min | 2.480s | 223.194us | 0 | 1 | 0.00 |
| V3 | max_value | rv_timer_max | 0.810s | 227.898us | 0 | 1 | 0.00 |
| V3 | stress_all_with_rand_reset | rv_timer_stress_all_with_rand_reset | 14.690s | 3.227ms | 0 | 1 | 0.00 |
| V3 | TOTAL | 0 | 3 | 0.00 | |||
| TOTAL | 15 | 19 | 78.95 |
UVM_FATAL (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state* (addr=*) == * has 2 failures:
Test rv_timer_min has 1 failures.
0.rv_timer_min.107083141205708577271523632580674056992011396318758656614010977929226432816241
Line 72, in log /nightly/current_run/scratch/master/rv_timer-sim-vcs/0.rv_timer_min/latest/run.log
UVM_FATAL @ 223193755 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0x394c2504) == 0x1
UVM_INFO @ 223193755 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test rv_timer_random_reset has 1 failures.
0.rv_timer_random_reset.107528541347864554848764610368965827140917882845101068310972298998030851612709
Line 72, in log /nightly/current_run/scratch/master/rv_timer-sim-vcs/0.rv_timer_random_reset/latest/run.log
UVM_FATAL @ 44041526963 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0x52d91504) == 0x1
UVM_INFO @ 44041526963 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_timer_scoreboard.sv:250) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) has 1 failures:
0.rv_timer_max.31308355416317379640910012333040195465632126180072132314999353149178455988201
Line 75, in log /nightly/current_run/scratch/master/rv_timer-sim-vcs/0.rv_timer_max/latest/run.log
UVM_ERROR @ 227897790 ps: (rv_timer_scoreboard.sv:250) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0])
UVM_INFO @ 227897790 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (cip_base_vseq.sv:1163) [rv_timer_common_vseq] Check failed (vseq_done) has 1 failures:
0.rv_timer_stress_all_with_rand_reset.76489627846254511256700609341338962734910667300812753915322554019003129426428
Line 248, in log /nightly/current_run/scratch/master/rv_timer-sim-vcs/0.rv_timer_stress_all_with_rand_reset/latest/run.log
UVM_FATAL @ 3227353286 ps: (cip_base_vseq.sv:1163) [uvm_test_top.env.virtual_sequencer.rv_timer_common_vseq] Check failed (vseq_done)
UVM_INFO @ 3227353286 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---