SPI_DEVICE/1R1W Simulation Results

Wednesday October 08 2025 17:04:29 UTC

GitHub Revision: e4ce7cf

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_device_flash_and_tpm	2.145m	87.387ms	1	1	100.00
V1	csr_hw_reset	spi_device_csr_hw_reset	0.940s	32.682us	1	1	100.00
V1	csr_rw	spi_device_csr_rw	1.150s	76.561us	1	1	100.00
V1	csr_bit_bash	spi_device_csr_bit_bash	28.230s	10.828ms	1	1	100.00
V1	csr_aliasing	spi_device_csr_aliasing	10.590s	615.851us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	spi_device_csr_mem_rw_with_rand_reset	2.080s	350.351us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_device_csr_rw	1.150s	76.561us	1	1	100.00
		spi_device_csr_aliasing	10.590s	615.851us	1	1	100.00
V1	mem_walk	spi_device_mem_walk	0.700s	18.856us	1	1	100.00
V1	mem_partial_access	spi_device_mem_partial_access	1.150s	19.354us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	csb_read	spi_device_csb_read	0.800s	23.648us	1	1	100.00
V2	mem_parity	spi_device_mem_parity	0.830s	1.223us	0	1	0.00
V2	mem_cfg	spi_device_ram_cfg	0.830s	3.560us	0	1	0.00
V2	tpm_read	spi_device_tpm_rw	4.460s	326.289us	1	1	100.00
V2	tpm_write	spi_device_tpm_rw	4.460s	326.289us	1	1	100.00
V2	tpm_hw_reg	spi_device_tpm_read_hw_reg	9.530s	38.192ms	1	1	100.00
		spi_device_tpm_sts_read	0.790s	287.110us	1	1	100.00
V2	tpm_fully_random_case	spi_device_tpm_all	16.170s	4.264ms	1	1	100.00
V2	pass_cmd_filtering	spi_device_pass_cmd_filtering	8.090s	20.057ms	1	1	100.00
		spi_device_flash_all	1.805m	26.509ms	1	1	100.00
V2	pass_addr_translation	spi_device_pass_addr_payload_swap	10.950s	17.358ms	1	1	100.00
		spi_device_flash_all	1.805m	26.509ms	1	1	100.00
V2	pass_payload_translation	spi_device_pass_addr_payload_swap	10.950s	17.358ms	1	1	100.00
		spi_device_flash_all	1.805m	26.509ms	1	1	100.00
V2	cmd_info_slots	spi_device_flash_all	1.805m	26.509ms	1	1	100.00
V2	cmd_read_status	spi_device_intercept	2.500s	108.584us	1	1	100.00
		spi_device_flash_all	1.805m	26.509ms	1	1	100.00
V2	cmd_read_jedec	spi_device_intercept	2.500s	108.584us	1	1	100.00
		spi_device_flash_all	1.805m	26.509ms	1	1	100.00
V2	cmd_read_sfdp	spi_device_intercept	2.500s	108.584us	1	1	100.00
		spi_device_flash_all	1.805m	26.509ms	1	1	100.00
V2	cmd_fast_read	spi_device_intercept	2.500s	108.584us	1	1	100.00
		spi_device_flash_all	1.805m	26.509ms	1	1	100.00
V2	cmd_read_pipeline	spi_device_intercept	2.500s	108.584us	1	1	100.00
		spi_device_flash_all	1.805m	26.509ms	1	1	100.00
V2	flash_cmd_upload	spi_device_upload	2.250s	495.684us	1	1	100.00
V2	mailbox_command	spi_device_mailbox	1.157m	11.487ms	1	1	100.00
V2	mailbox_cross_outside_command	spi_device_mailbox	1.157m	11.487ms	1	1	100.00
V2	mailbox_cross_inside_command	spi_device_mailbox	1.157m	11.487ms	1	1	100.00
V2	cmd_read_buffer	spi_device_flash_mode	24.260s	8.101ms	1	1	100.00
		spi_device_read_buffer_direct	2.490s	273.482us	1	1	100.00
V2	cmd_dummy_cycle	spi_device_mailbox	1.157m	11.487ms	1	1	100.00
		spi_device_flash_all	1.805m	26.509ms	1	1	100.00
V2	quad_spi	spi_device_flash_all	1.805m	26.509ms	1	1	100.00
V2	dual_spi	spi_device_flash_all	1.805m	26.509ms	1	1	100.00
V2	4b_3b_feature	spi_device_cfg_cmd	2.650s	636.332us	1	1	100.00
V2	write_enable_disable	spi_device_cfg_cmd	2.650s	636.332us	1	1	100.00
V2	TPM_with_flash_or_passthrough_mode	spi_device_flash_and_tpm	2.145m	87.387ms	1	1	100.00
V2	tpm_and_flash_trans_with_min_inactive_time	spi_device_flash_and_tpm_min_idle	2.631m	22.758ms	1	1	100.00
V2	stress_all	spi_device_stress_all	6.665m	59.490ms	1	1	100.00
V2	alert_test	spi_device_alert_test	1.000s	46.054us	1	1	100.00
V2	intr_test	spi_device_intr_test	0.670s	29.532us	1	1	100.00
V2	tl_d_oob_addr_access	spi_device_tl_errors	1.700s	71.968us	1	1	100.00
V2	tl_d_illegal_access	spi_device_tl_errors	1.700s	71.968us	1	1	100.00
V2	tl_d_outstanding_access	spi_device_csr_hw_reset	0.940s	32.682us	1	1	100.00
		spi_device_csr_rw	1.150s	76.561us	1	1	100.00
		spi_device_csr_aliasing	10.590s	615.851us	1	1	100.00
		spi_device_same_csr_outstanding	1.480s	59.888us	1	1	100.00
V2	tl_d_partial_access	spi_device_csr_hw_reset	0.940s	32.682us	1	1	100.00
		spi_device_csr_rw	1.150s	76.561us	1	1	100.00
		spi_device_csr_aliasing	10.590s	615.851us	1	1	100.00
		spi_device_same_csr_outstanding	1.480s	59.888us	1	1	100.00
V2		TOTAL			20	22	90.91
V2S	tl_intg_err	spi_device_sec_cm	1.180s	46.107us	1	1	100.00
		spi_device_tl_intg_err	8.230s	212.946us	1	1	100.00
V2S	sec_cm_bus_integrity	spi_device_tl_intg_err	8.230s	212.946us	1	1	100.00
V2S		TOTAL			2	2	100.00
	Unmapped tests	spi_device_flash_mode_ignore_cmds	34.990s	13.960ms	1	1	100.00
		TOTAL			31	33	93.94

Failure Buckets

• UVM_ERROR (uvm_hdl_vcs.c:1035) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[*]) has 1 failures:

  • Test spi_device_mem_parity has 1 failures.

    • 0.spi_device_mem_parity.70759512170529429071263494411811531736879421451870645023854807860473319606440
      Line 73, in log /nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/0.spi_device_mem_parity/latest/run.log

        UVM_ERROR @   1033879 ps: (uvm_hdl_vcs.c:1035) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[3])
         Either the name is incorrect, or you may not have PLI/ACC visibility to that name
        UVM_ERROR @   1033879 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
        UVM_ERROR @   1033879 ps: (uvm_hdl_vcs.c:1185) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[899])
         Either the name is incorrect, or you may not have PLI/ACC visibility to that name
      

• UVM_ERROR (spi_device_ram_cfg_vseq.sv:27) [spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (* [*] vs * [*]) has 1 failures:

  • Test spi_device_ram_cfg has 1 failures.

    • 0.spi_device_ram_cfg.91819380664272407012008719161982767986063346994224868453335127712410231298213
      Line 73, in log /nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/0.spi_device_ram_cfg/latest/run.log

        UVM_ERROR @   1070216 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x14f5b [10100111101011011] vs 0x0 [0])
        UVM_ERROR @   1138216 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xdfa533 [110111111010010100110011] vs 0x0 [0])
        UVM_ERROR @   1217216 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xabde85 [101010111101111010000101] vs 0x0 [0])
        UVM_ERROR @   1286216 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x7b55dd [11110110101010111011101] vs 0x0 [0])
        UVM_ERROR @   1292216 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xe987dd [111010011000011111011101] vs 0x0 [0])