SPI_DEVICE/2P Simulation Results

Wednesday October 08 2025 17:04:29 UTC

GitHub Revision: e4ce7cf

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke spi_device_flash_and_tpm 23.410s 9.391ms 1 1 100.00
V1 csr_hw_reset spi_device_csr_hw_reset 1.100s 22.715us 1 1 100.00
V1 csr_rw spi_device_csr_rw 1.230s 154.531us 1 1 100.00
V1 csr_bit_bash spi_device_csr_bit_bash 25.300s 11.244ms 1 1 100.00
V1 csr_aliasing spi_device_csr_aliasing 11.060s 3.029ms 1 1 100.00
V1 csr_mem_rw_with_rand_reset spi_device_csr_mem_rw_with_rand_reset 2.060s 78.015us 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr spi_device_csr_rw 1.230s 154.531us 1 1 100.00
spi_device_csr_aliasing 11.060s 3.029ms 1 1 100.00
V1 mem_walk spi_device_mem_walk 0.820s 32.816us 1 1 100.00
V1 mem_partial_access spi_device_mem_partial_access 1.280s 70.778us 1 1 100.00
V1 TOTAL 8 8 100.00
V2 csb_read spi_device_csb_read 0.890s 60.588us 1 1 100.00
V2 mem_parity spi_device_mem_parity 1.110s 24.141us 1 1 100.00
V2 mem_cfg spi_device_ram_cfg 0.940s 69.022us 1 1 100.00
V2 tpm_read spi_device_tpm_rw 1.410s 94.449us 1 1 100.00
V2 tpm_write spi_device_tpm_rw 1.410s 94.449us 1 1 100.00
V2 tpm_hw_reg spi_device_tpm_read_hw_reg 4.380s 1.221ms 1 1 100.00
spi_device_tpm_sts_read 0.720s 18.227us 1 1 100.00
V2 tpm_fully_random_case spi_device_tpm_all 9.060s 3.689ms 1 1 100.00
V2 pass_cmd_filtering spi_device_pass_cmd_filtering 3.950s 619.487us 1 1 100.00
spi_device_flash_all 1.027m 15.526ms 1 1 100.00
V2 pass_addr_translation spi_device_pass_addr_payload_swap 5.160s 2.866ms 1 1 100.00
spi_device_flash_all 1.027m 15.526ms 1 1 100.00
V2 pass_payload_translation spi_device_pass_addr_payload_swap 5.160s 2.866ms 1 1 100.00
spi_device_flash_all 1.027m 15.526ms 1 1 100.00
V2 cmd_info_slots spi_device_flash_all 1.027m 15.526ms 1 1 100.00
V2 cmd_read_status spi_device_intercept 5.200s 1.253ms 1 1 100.00
spi_device_flash_all 1.027m 15.526ms 1 1 100.00
V2 cmd_read_jedec spi_device_intercept 5.200s 1.253ms 1 1 100.00
spi_device_flash_all 1.027m 15.526ms 1 1 100.00
V2 cmd_read_sfdp spi_device_intercept 5.200s 1.253ms 1 1 100.00
spi_device_flash_all 1.027m 15.526ms 1 1 100.00
V2 cmd_fast_read spi_device_intercept 5.200s 1.253ms 1 1 100.00
spi_device_flash_all 1.027m 15.526ms 1 1 100.00
V2 cmd_read_pipeline spi_device_intercept 5.200s 1.253ms 1 1 100.00
spi_device_flash_all 1.027m 15.526ms 1 1 100.00
V2 flash_cmd_upload spi_device_upload 4.940s 2.663ms 1 1 100.00
V2 mailbox_command spi_device_mailbox 6.930s 1.507ms 1 1 100.00
V2 mailbox_cross_outside_command spi_device_mailbox 6.930s 1.507ms 1 1 100.00
V2 mailbox_cross_inside_command spi_device_mailbox 6.930s 1.507ms 1 1 100.00
V2 cmd_read_buffer spi_device_flash_mode 2.980s 257.383us 1 1 100.00
spi_device_read_buffer_direct 2.970s 138.635us 1 1 100.00
V2 cmd_dummy_cycle spi_device_mailbox 6.930s 1.507ms 1 1 100.00
spi_device_flash_all 1.027m 15.526ms 1 1 100.00
V2 quad_spi spi_device_flash_all 1.027m 15.526ms 1 1 100.00
V2 dual_spi spi_device_flash_all 1.027m 15.526ms 1 1 100.00
V2 4b_3b_feature spi_device_cfg_cmd 7.290s 1.118ms 1 1 100.00
V2 write_enable_disable spi_device_cfg_cmd 7.290s 1.118ms 1 1 100.00
V2 TPM_with_flash_or_passthrough_mode spi_device_flash_and_tpm 23.410s 9.391ms 1 1 100.00
V2 tpm_and_flash_trans_with_min_inactive_time spi_device_flash_and_tpm_min_idle 59.850s 4.099ms 1 1 100.00
V2 stress_all spi_device_stress_all 45.390s 11.479ms 1 1 100.00
V2 alert_test spi_device_alert_test 0.780s 25.012us 1 1 100.00
V2 intr_test spi_device_intr_test 0.880s 22.272us 1 1 100.00
V2 tl_d_oob_addr_access spi_device_tl_errors 4.340s 246.567us 1 1 100.00
V2 tl_d_illegal_access spi_device_tl_errors 4.340s 246.567us 1 1 100.00
V2 tl_d_outstanding_access spi_device_csr_hw_reset 1.100s 22.715us 1 1 100.00
spi_device_csr_rw 1.230s 154.531us 1 1 100.00
spi_device_csr_aliasing 11.060s 3.029ms 1 1 100.00
spi_device_same_csr_outstanding 2.200s 144.993us 1 1 100.00
V2 tl_d_partial_access spi_device_csr_hw_reset 1.100s 22.715us 1 1 100.00
spi_device_csr_rw 1.230s 154.531us 1 1 100.00
spi_device_csr_aliasing 11.060s 3.029ms 1 1 100.00
spi_device_same_csr_outstanding 2.200s 144.993us 1 1 100.00
V2 TOTAL 22 22 100.00
V2S tl_intg_err spi_device_sec_cm 1.250s 180.114us 1 1 100.00
spi_device_tl_intg_err 9.320s 578.278us 1 1 100.00
V2S sec_cm_bus_integrity spi_device_tl_intg_err 9.320s 578.278us 1 1 100.00
V2S TOTAL 2 2 100.00
Unmapped tests spi_device_flash_mode_ignore_cmds 2.084m 31.725ms 1 1 100.00
TOTAL 33 33 100.00