SPI_HOST Simulation Results

Wednesday October 08 2025 17:04:29 UTC

GitHub Revision: e4ce7cf

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_host_smoke	2.000s	109.304us	1	1	100.00
V1	csr_hw_reset	spi_host_csr_hw_reset	2.000s	42.500us	1	1	100.00
V1	csr_rw	spi_host_csr_rw	2.000s	123.430us	1	1	100.00
V1	csr_bit_bash	spi_host_csr_bit_bash	2.000s	124.680us	1	1	100.00
V1	csr_aliasing	spi_host_csr_aliasing	1.000s	29.837us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	spi_host_csr_mem_rw_with_rand_reset	2.000s	31.576us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_host_csr_rw	2.000s	123.430us	1	1	100.00
		spi_host_csr_aliasing	1.000s	29.837us	1	1	100.00
V1	mem_walk	spi_host_mem_walk	1.000s	14.521us	1	1	100.00
V1	mem_partial_access	spi_host_mem_partial_access	1.000s	22.378us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	performance	spi_host_performance	2.000s	184.515us	1	1	100.00
V2	error_event_intr	spi_host_overflow_underflow	2.000s	201.309us	1	1	100.00
		spi_host_error_cmd	2.000s	19.685us	1	1	100.00
		spi_host_event	7.000s	991.395us	1	1	100.00
V2	clock_rate	spi_host_speed	2.000s	79.455us	1	1	100.00
V2	speed	spi_host_speed	2.000s	79.455us	1	1	100.00
V2	chip_select_timing	spi_host_speed	2.000s	79.455us	1	1	100.00
V2	sw_reset	spi_host_sw_reset	7.000s	823.751us	1	1	100.00
V2	passthrough_mode	spi_host_passthrough_mode	1.000s	22.949us	1	1	100.00
V2	cpol_cpha	spi_host_speed	2.000s	79.455us	1	1	100.00
V2	full_cycle	spi_host_speed	2.000s	79.455us	1	1	100.00
V2	duplex	spi_host_smoke	2.000s	109.304us	1	1	100.00
V2	tx_rx_only	spi_host_smoke	2.000s	109.304us	1	1	100.00
V2	stress_all	spi_host_stress_all	4.000s	215.733us	1	1	100.00
V2	spien	spi_host_spien	4.000s	482.315us	1	1	100.00
V2	stall	spi_host_status_stall	17.783m	1.000s	0	1	0.00
V2	Idlecsbactive	spi_host_idlecsbactive	3.000s	93.366us	1	1	100.00
V2	data_fifo_status	spi_host_overflow_underflow	2.000s	201.309us	1	1	100.00
V2	alert_test	spi_host_alert_test	1.000s	26.120us	1	1	100.00
V2	intr_test	spi_host_intr_test	1.000s	29.203us	1	1	100.00
V2	tl_d_oob_addr_access	spi_host_tl_errors	2.000s	312.238us	1	1	100.00
V2	tl_d_illegal_access	spi_host_tl_errors	2.000s	312.238us	1	1	100.00
V2	tl_d_outstanding_access	spi_host_csr_hw_reset	2.000s	42.500us	1	1	100.00
		spi_host_csr_rw	2.000s	123.430us	1	1	100.00
		spi_host_csr_aliasing	1.000s	29.837us	1	1	100.00
		spi_host_same_csr_outstanding	1.000s	24.802us	1	1	100.00
V2	tl_d_partial_access	spi_host_csr_hw_reset	2.000s	42.500us	1	1	100.00
		spi_host_csr_rw	2.000s	123.430us	1	1	100.00
		spi_host_csr_aliasing	1.000s	29.837us	1	1	100.00
		spi_host_same_csr_outstanding	1.000s	24.802us	1	1	100.00
V2		TOTAL			14	15	93.33
V2S	tl_intg_err	spi_host_tl_intg_err	2.000s	196.043us	1	1	100.00
		spi_host_sec_cm	1.000s	76.882us	1	1	100.00
V2S	sec_cm_bus_integrity	spi_host_tl_intg_err	2.000s	196.043us	1	1	100.00
V2S		TOTAL			2	2	100.00
	Unmapped tests	spi_host_upper_range_clkdiv	5.550m	11.517ms	1	1	100.00
		TOTAL			25	26	96.15

Failure Buckets

• UVM_FATAL (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
  • Test spi_host_status_stall has 1 failures.

    • 0.spi_host_status_stall.88308966490471616474756853239714882610592223630386531632440310483034400786924
      Line 6761, in log /nightly/current_run/scratch/master/spi_host-sim-xcelium/0.spi_host_status_stall/latest/run.log

        UVM_FATAL @ 1000000000000 ps: (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of 1000000000000 ps hit, indicating a probable testbench issue
        UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---