SRAM_CTRL/MAIN Simulation Results

Wednesday October 08 2025 17:04:29 UTC

GitHub Revision: e4ce7cf

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	22.230s	738.197us	1	1	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	0.860s	44.525us	1	1	100.00
V1	csr_rw	sram_ctrl_csr_rw	0.840s	13.987us	1	1	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	1.450s	763.594us	1	1	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	0.880s	21.676us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	2.100s	360.590us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	0.840s	13.987us	1	1	100.00
		sram_ctrl_csr_aliasing	0.880s	21.676us	1	1	100.00
V1	mem_walk	sram_ctrl_mem_walk	3.153m	4.080ms	1	1	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	56.730s	10.661ms	1	1	100.00
V1		TOTAL			8	8	100.00
V2	multiple_keys	sram_ctrl_multiple_keys	5.777m	26.329ms	1	1	100.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	1.824m	2.103ms	1	1	100.00
V2	bijection	sram_ctrl_bijection	30.700m	206.778ms	1	1	100.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	11.599m	83.826ms	1	1	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	19.270s	4.625ms	1	1	100.00
V2	executable	sram_ctrl_executable	7.703m	42.941ms	1	1	100.00
V2	partial_access	sram_ctrl_partial_access	10.620s	9.977ms	1	1	100.00
		sram_ctrl_partial_access_b2b	2.371m	5.997ms	1	1	100.00
V2	max_throughput	sram_ctrl_max_throughput	48.840s	4.716ms	1	1	100.00
		sram_ctrl_throughput_w_partial_write	7.340s	8.522ms	1	1	100.00
		sram_ctrl_throughput_w_readback	44.890s	912.379us	1	1	100.00
V2	regwen	sram_ctrl_regwen	6.368m	41.781ms	1	1	100.00
V2	ram_cfg	sram_ctrl_ram_cfg	3.710s	362.172us	1	1	100.00
V2	stress_all	sram_ctrl_stress_all	1.902h	456.112ms	1	1	100.00
V2	alert_test	sram_ctrl_alert_test	0.920s	16.731us	1	1	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	2.670s	370.672us	1	1	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	2.670s	370.672us	1	1	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	0.860s	44.525us	1	1	100.00
		sram_ctrl_csr_rw	0.840s	13.987us	1	1	100.00
		sram_ctrl_csr_aliasing	0.880s	21.676us	1	1	100.00
		sram_ctrl_same_csr_outstanding	0.920s	20.517us	1	1	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	0.860s	44.525us	1	1	100.00
		sram_ctrl_csr_rw	0.840s	13.987us	1	1	100.00
		sram_ctrl_csr_aliasing	0.880s	21.676us	1	1	100.00
		sram_ctrl_same_csr_outstanding	0.920s	20.517us	1	1	100.00
V2		TOTAL			17	17	100.00
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	20.620s	3.988ms	1	1	100.00
V2S	tl_intg_err	sram_ctrl_sec_cm	0.790s	3.766us	0	1	0.00
		sram_ctrl_tl_intg_err	2.600s	422.537us	1	1	100.00
V2S	prim_count_check	sram_ctrl_sec_cm	0.790s	3.766us	0	1	0.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	2.600s	422.537us	1	1	100.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	6.368m	41.781ms	1	1	100.00
V2S	sec_cm_readback_config_regwen	sram_ctrl_regwen	6.368m	41.781ms	1	1	100.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	0.840s	13.987us	1	1	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	7.703m	42.941ms	1	1	100.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	7.703m	42.941ms	1	1	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	7.703m	42.941ms	1	1	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	19.270s	4.625ms	1	1	100.00
V2S	sec_cm_prim_ram_ctrl_mubi	sram_ctrl_mubi_enc_err	5.590s	696.224us	1	1	100.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	20.620s	3.988ms	1	1	100.00
V2S	sec_cm_mem_readback	sram_ctrl_readback_err	3.840s	669.985us	1	1	100.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	22.230s	738.197us	1	1	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	22.230s	738.197us	1	1	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	7.703m	42.941ms	1	1	100.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	0.790s	3.766us	0	1	0.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	19.270s	4.625ms	1	1	100.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	0.790s	3.766us	0	1	0.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	0.790s	3.766us	0	1	0.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	22.230s	738.197us	1	1	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	0.790s	3.766us	0	1	0.00
V2S		TOTAL			4	5	80.00
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	13.960s	1.161ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			30	31	96.77

Failure Buckets

• UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: * has 1 failures:
  • Test sram_ctrl_sec_cm has 1 failures.

    • 0.sram_ctrl_sec_cm.5115056510546142535085756099338863423733153725997827246865866884272289501104
      Line 97, in log /nightly/current_run/scratch/master/sram_ctrl_main-sim-vcs/0.sram_ctrl_sec_cm/latest/run.log

        UVM_ERROR @   3765634 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0
        UVM_INFO @   3765634 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---