SRAM_CTRL/RET Simulation Results

Wednesday October 08 2025 17:04:29 UTC

GitHub Revision: e4ce7cf

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	4.520s	345.878us	1	1	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	0.940s	87.007us	1	1	100.00
V1	csr_rw	sram_ctrl_csr_rw	0.760s	13.445us	1	1	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	1.710s	117.088us	1	1	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	0.800s	21.529us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	1.090s	95.134us	0	1	0.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	0.760s	13.445us	1	1	100.00
		sram_ctrl_csr_aliasing	0.800s	21.529us	1	1	100.00
V1	mem_walk	sram_ctrl_mem_walk	5.060s	1.379ms	1	1	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	4.350s	367.280us	1	1	100.00
V1		TOTAL			7	8	87.50
V2	multiple_keys	sram_ctrl_multiple_keys	7.483m	6.850ms	1	1	100.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	5.278m	21.859ms	1	1	100.00
V2	bijection	sram_ctrl_bijection	17.960s	714.171us	1	1	100.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	3.025m	11.725ms	1	1	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	4.070s	433.297us	1	1	100.00
V2	executable	sram_ctrl_executable	1.247m	431.827us	1	1	100.00
V2	partial_access	sram_ctrl_partial_access	1.540s	139.356us	1	1	100.00
		sram_ctrl_partial_access_b2b	5.771m	66.999ms	1	1	100.00
V2	max_throughput	sram_ctrl_max_throughput	47.780s	1.827ms	1	1	100.00
		sram_ctrl_throughput_w_partial_write	27.000s	369.926us	1	1	100.00
		sram_ctrl_throughput_w_readback	4.910s	93.044us	1	1	100.00
V2	regwen	sram_ctrl_regwen	10.235m	72.794ms	1	1	100.00
V2	ram_cfg	sram_ctrl_ram_cfg	0.780s	26.070us	1	1	100.00
V2	stress_all	sram_ctrl_stress_all	16.060m	106.352ms	1	1	100.00
V2	alert_test	sram_ctrl_alert_test	0.730s	16.348us	1	1	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	2.210s	70.942us	1	1	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	2.210s	70.942us	1	1	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	0.940s	87.007us	1	1	100.00
		sram_ctrl_csr_rw	0.760s	13.445us	1	1	100.00
		sram_ctrl_csr_aliasing	0.800s	21.529us	1	1	100.00
		sram_ctrl_same_csr_outstanding	0.770s	33.480us	1	1	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	0.940s	87.007us	1	1	100.00
		sram_ctrl_csr_rw	0.760s	13.445us	1	1	100.00
		sram_ctrl_csr_aliasing	0.800s	21.529us	1	1	100.00
		sram_ctrl_same_csr_outstanding	0.770s	33.480us	1	1	100.00
V2		TOTAL			17	17	100.00
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	2.660s	769.424us	1	1	100.00
V2S	tl_intg_err	sram_ctrl_sec_cm	0.930s	9.009us	0	1	0.00
		sram_ctrl_tl_intg_err	2.500s	548.542us	1	1	100.00
V2S	prim_count_check	sram_ctrl_sec_cm	0.930s	9.009us	0	1	0.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	2.500s	548.542us	1	1	100.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	10.235m	72.794ms	1	1	100.00
V2S	sec_cm_readback_config_regwen	sram_ctrl_regwen	10.235m	72.794ms	1	1	100.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	0.760s	13.445us	1	1	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	1.247m	431.827us	1	1	100.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	1.247m	431.827us	1	1	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	1.247m	431.827us	1	1	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	4.070s	433.297us	1	1	100.00
V2S	sec_cm_prim_ram_ctrl_mubi	sram_ctrl_mubi_enc_err	1.170s	122.477us	1	1	100.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	2.660s	769.424us	1	1	100.00
V2S	sec_cm_mem_readback	sram_ctrl_readback_err	1.020s	172.448us	1	1	100.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	4.520s	345.878us	1	1	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	4.520s	345.878us	1	1	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	1.247m	431.827us	1	1	100.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	0.930s	9.009us	0	1	0.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	4.070s	433.297us	1	1	100.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	0.930s	9.009us	0	1	0.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	0.930s	9.009us	0	1	0.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	4.520s	345.878us	1	1	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	0.930s	9.009us	0	1	0.00
V2S		TOTAL			4	5	80.00
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	3.179m	812.424us	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			29	31	93.55

Failure Buckets

• UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: * has 1 failures:

  • Test sram_ctrl_sec_cm has 1 failures.

    • 0.sram_ctrl_sec_cm.56247461486273280927754130473805748676497185449117101170883506544636136302322
      Line 99, in log /nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/0.sram_ctrl_sec_cm/latest/run.log

        UVM_ERROR @   9009301 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0
        UVM_INFO @   9009301 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.status.init_done reset value: * has 1 failures:

  • Test sram_ctrl_csr_mem_rw_with_rand_reset has 1 failures.

    • 0.sram_ctrl_csr_mem_rw_with_rand_reset.27593498982158210773294956602236656927946165645225000179843020816027886545978
      Line 95, in log /nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/0.sram_ctrl_csr_mem_rw_with_rand_reset/latest/run.log

        UVM_ERROR @  95134448 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: sram_ctrl_regs_reg_block.status.init_done reset value: 0x0
        UVM_INFO @  95134448 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---