SYSRST_CTRL Simulation Results

Wednesday October 08 2025 17:04:29 UTC

GitHub Revision: e4ce7cf

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke sysrst_ctrl_smoke 4.810s 2.113ms 1 1 100.00
V1 input_output_inverted sysrst_ctrl_in_out_inverted 3.430s 2.460ms 1 1 100.00
V1 combo_detect_ec_rst sysrst_ctrl_combo_detect_ec_rst 5.310s 2.404ms 1 1 100.00
V1 combo_detect_ec_rst_with_pre_cond sysrst_ctrl_combo_detect_ec_rst_with_pre_cond 2.300s 2.314ms 1 1 100.00
V1 csr_hw_reset sysrst_ctrl_csr_hw_reset 8.960s 4.010ms 1 1 100.00
V1 csr_rw sysrst_ctrl_csr_rw 5.380s 2.034ms 1 1 100.00
V1 csr_bit_bash sysrst_ctrl_csr_bit_bash 18.160s 39.158ms 1 1 100.00
V1 csr_aliasing sysrst_ctrl_csr_aliasing 6.060s 3.185ms 1 1 100.00
V1 csr_mem_rw_with_rand_reset sysrst_ctrl_csr_mem_rw_with_rand_reset 2.190s 2.326ms 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr sysrst_ctrl_csr_rw 5.380s 2.034ms 1 1 100.00
sysrst_ctrl_csr_aliasing 6.060s 3.185ms 1 1 100.00
V1 TOTAL 9 9 100.00
V2 combo_detect sysrst_ctrl_combo_detect 1.064m 33.534ms 1 1 100.00
V2 combo_detect_with_pre_cond sysrst_ctrl_combo_detect_with_pre_cond 6.584m 198.734ms 1 1 100.00
V2 auto_block_key_outputs sysrst_ctrl_auto_blk_key_output 7.130s 3.599ms 1 1 100.00
V2 keyboard_input_triggered_interrupt sysrst_ctrl_edge_detect 1.800s 4.655ms 1 1 100.00
V2 pin_output_keyboard_inversion_control sysrst_ctrl_pin_override_test 5.060s 2.509ms 1 1 100.00
V2 pin_input_value_accessibility sysrst_ctrl_pin_access_test 2.690s 2.092ms 1 1 100.00
V2 ec_power_on_reset sysrst_ctrl_ec_pwr_on_rst 2.530s 3.944ms 1 1 100.00
V2 flash_write_protect_output sysrst_ctrl_flash_wr_prot_out 2.880s 2.629ms 1 1 100.00
V2 ultra_low_power_test sysrst_ctrl_ultra_low_pwr 7.090s 6.409ms 1 1 100.00
V2 sysrst_ctrl_feature_disable sysrst_ctrl_feature_disable 16.650s 37.897ms 1 1 100.00
V2 stress_all sysrst_ctrl_stress_all 6.230s 11.379ms 1 1 100.00
V2 alert_test sysrst_ctrl_alert_test 4.520s 2.013ms 1 1 100.00
V2 intr_test sysrst_ctrl_intr_test 4.470s 2.018ms 1 1 100.00
V2 tl_d_oob_addr_access sysrst_ctrl_tl_errors 3.370s 2.368ms 1 1 100.00
V2 tl_d_illegal_access sysrst_ctrl_tl_errors 3.370s 2.368ms 1 1 100.00
V2 tl_d_outstanding_access sysrst_ctrl_csr_hw_reset 8.960s 4.010ms 1 1 100.00
sysrst_ctrl_csr_rw 5.380s 2.034ms 1 1 100.00
sysrst_ctrl_csr_aliasing 6.060s 3.185ms 1 1 100.00
sysrst_ctrl_same_csr_outstanding 7.800s 7.763ms 1 1 100.00
V2 tl_d_partial_access sysrst_ctrl_csr_hw_reset 8.960s 4.010ms 1 1 100.00
sysrst_ctrl_csr_rw 5.380s 2.034ms 1 1 100.00
sysrst_ctrl_csr_aliasing 6.060s 3.185ms 1 1 100.00
sysrst_ctrl_same_csr_outstanding 7.800s 7.763ms 1 1 100.00
V2 TOTAL 15 15 100.00
V2S tl_intg_err sysrst_ctrl_sec_cm 10.700s 22.103ms 1 1 100.00
sysrst_ctrl_tl_intg_err 1.339m 42.506ms 1 1 100.00
V2S sec_cm_bus_integrity sysrst_ctrl_tl_intg_err 1.339m 42.506ms 1 1 100.00
V2S TOTAL 2 2 100.00
V3 stress_all_with_rand_reset sysrst_ctrl_stress_all_with_rand_reset 14.940s 7.707ms 1 1 100.00
V3 TOTAL 1 1 100.00
TOTAL 27 27 100.00