UART Simulation Results

Wednesday October 08 2025 17:04:29 UTC

GitHub Revision: e4ce7cf

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	uart_smoke	8.640s	5.679ms	1	1	100.00
V1	csr_hw_reset	uart_csr_hw_reset	0.650s	12.994us	1	1	100.00
V1	csr_rw	uart_csr_rw	0.780s	12.110us	1	1	100.00
V1	csr_bit_bash	uart_csr_bit_bash	1.330s	95.568us	1	1	100.00
V1	csr_aliasing	uart_csr_aliasing	0.790s	46.120us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	uart_csr_mem_rw_with_rand_reset	1.310s	25.914us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	uart_csr_rw	0.780s	12.110us	1	1	100.00
		uart_csr_aliasing	0.790s	46.120us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	base_random_seq	uart_tx_rx	25.900s	21.605ms	1	1	100.00
V2	parity	uart_smoke	8.640s	5.679ms	1	1	100.00
		uart_tx_rx	25.900s	21.605ms	1	1	100.00
V2	parity_error	uart_intr	30.480s	32.305ms	1	1	100.00
		uart_rx_parity_err	23.070s	58.147ms	1	1	100.00
V2	watermark	uart_tx_rx	25.900s	21.605ms	1	1	100.00
		uart_intr	30.480s	32.305ms	1	1	100.00
V2	fifo_full	uart_fifo_full	34.000s	22.766ms	1	1	100.00
V2	fifo_overflow	uart_fifo_overflow	18.400s	30.064ms	1	1	100.00
V2	fifo_reset	uart_fifo_reset	58.260s	119.830ms	1	1	100.00
V2	rx_frame_err	uart_intr	30.480s	32.305ms	1	1	100.00
V2	rx_break_err	uart_intr	30.480s	32.305ms	1	1	100.00
V2	rx_timeout	uart_intr	30.480s	32.305ms	1	1	100.00
V2	perf	uart_perf	8.585m	12.629ms	1	1	100.00
V2	sys_loopback	uart_loopback	10.070s	7.503ms	1	1	100.00
V2	line_loopback	uart_loopback	10.070s	7.503ms	1	1	100.00
V2	rx_noise_filter	uart_noise_filter	4.210s	3.070ms	0	1	0.00
V2	rx_start_bit_filter	uart_rx_start_bit_filter	1.930s	4.195ms	1	1	100.00
V2	tx_overide	uart_tx_ovrd	7.030s	7.285ms	1	1	100.00
V2	rx_oversample	uart_rx_oversample	8.050s	5.331ms	1	1	100.00
V2	long_b2b_transfer	uart_long_xfer_wo_dly	7.623m	83.206ms	1	1	100.00
V2	stress_all	uart_stress_all	1.397m	261.846ms	1	1	100.00
V2	alert_test	uart_alert_test	0.680s	57.599us	1	1	100.00
V2	intr_test	uart_intr_test	0.570s	13.356us	1	1	100.00
V2	tl_d_oob_addr_access	uart_tl_errors	1.900s	442.474us	1	1	100.00
V2	tl_d_illegal_access	uart_tl_errors	1.900s	442.474us	1	1	100.00
V2	tl_d_outstanding_access	uart_csr_hw_reset	0.650s	12.994us	1	1	100.00
		uart_csr_rw	0.780s	12.110us	1	1	100.00
		uart_csr_aliasing	0.790s	46.120us	1	1	100.00
		uart_same_csr_outstanding	0.750s	29.591us	1	1	100.00
V2	tl_d_partial_access	uart_csr_hw_reset	0.650s	12.994us	1	1	100.00
		uart_csr_rw	0.780s	12.110us	1	1	100.00
		uart_csr_aliasing	0.790s	46.120us	1	1	100.00
		uart_same_csr_outstanding	0.750s	29.591us	1	1	100.00
V2		TOTAL			17	18	94.44
V2S	tl_intg_err	uart_sec_cm	0.940s	239.655us	1	1	100.00
		uart_tl_intg_err	1.160s	2.128ms	1	1	100.00
V2S	sec_cm_bus_integrity	uart_tl_intg_err	1.160s	2.128ms	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	stress_all_with_rand_reset	uart_stress_all_with_rand_reset	37.200s	10.769ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			26	27	96.30

Failure Buckets

• UVM_ERROR (uart_scoreboard.sv:501) scoreboard [scoreboard] rxlvl mismatch exp: * (+/-1), act: *, clk_pulses: * has 1 failures:
  • Test uart_noise_filter has 1 failures.

    • 0.uart_noise_filter.92393053763504908804863925761232839803531761979838623831622984190880033312688
      Line 72, in log /nightly/current_run/scratch/master/uart-sim-vcs/0.uart_noise_filter/latest/run.log

        UVM_ERROR @ 2110457631 ps: (uart_scoreboard.sv:501) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 0 (+/-1), act: 1,                                 clk_pulses: 0
        UVM_ERROR @ 2110467631 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty
        UVM_ERROR @ 2110477631 ps: (uart_scoreboard.sv:531) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (12 [0xc] vs 239 [0xef]) reg name: uart_reg_block.rdata
        UVM_ERROR @ 2178737631 ps: (uart_scoreboard.sv:501) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 0 (+/-1), act: 1,                                 clk_pulses: 0
        UVM_ERROR @ 2178747631 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty