CHIP Simulation Results

Wednesday October 08 2025 17:04:29 UTC

GitHub Revision: `e4ce7cf`

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	chip_sw_example_tests	chip_sw_example_flash	2.239m	2.962ms	1	1	100.00
		chip_sw_example_rom	1.241m	2.621ms	1	1	100.00
		chip_sw_example_manufacturer	1.966m	2.736ms	1	1	100.00
		chip_sw_example_concurrency	2.055m	3.177ms	1	1	100.00
V1	csr_hw_reset	chip_csr_hw_reset	2.109m	4.144ms	1	1	100.00
V1	csr_rw	chip_csr_rw	3.468m	3.978ms	1	1	100.00
V1	csr_bit_bash	chip_csr_bit_bash	11.150m	8.823ms	1	1	100.00
V1	csr_aliasing	chip_csr_aliasing	1.242h	36.387ms	1	1	100.00
V1	csr_mem_rw_with_rand_reset	chip_csr_mem_rw_with_rand_reset	48.550s	2.257ms	0	1	0.00
V1	regwen_csr_and_corresponding_lockable_csr	chip_csr_aliasing	1.242h	36.387ms	1	1	100.00
		chip_csr_rw	3.468m	3.978ms	1	1	100.00
V1	xbar_smoke	xbar_smoke	5.090s	47.768us	1	1	100.00
V1	chip_sw_gpio_out	chip_sw_gpio	5.465m	4.416ms	1	1	100.00
V1	chip_sw_gpio_in	chip_sw_gpio	5.465m	4.416ms	1	1	100.00
V1	chip_sw_gpio_irq	chip_sw_gpio	5.465m	4.416ms	1	1	100.00
V1	chip_sw_uart_tx_rx	chip_sw_uart_tx_rx	6.073m	4.283ms	1	1	100.00
V1	chip_sw_uart_rx_overflow	chip_sw_uart_tx_rx	6.073m	4.283ms	1	1	100.00
		chip_sw_uart_tx_rx_idx1	6.138m	4.682ms	1	1	100.00
		chip_sw_uart_tx_rx_idx2	5.455m	4.578ms	1	1	100.00
		chip_sw_uart_tx_rx_idx3	5.653m	4.209ms	1	1	100.00
V1	chip_sw_uart_baud_rate	chip_sw_uart_rand_baudrate	17.532m	8.802ms	1	1	100.00
V1	chip_sw_uart_tx_rx_alt_clk_freq	chip_sw_uart_tx_rx_alt_clk_freq	17.797m	8.475ms	1	1	100.00
		chip_sw_uart_tx_rx_alt_clk_freq_low_speed	12.018m	9.190ms	1	1	100.00
V1		TOTAL			17	18	94.44
V2	chip_pin_mux	chip_padctrl_attributes	2.212m	4.172ms	1	1	100.00
V2	chip_padctrl_attributes	chip_padctrl_attributes	2.212m	4.172ms	1	1	100.00
V2	chip_sw_sleep_pin_mio_dio_val	chip_sw_sleep_pin_mio_dio_val	3.004m	3.066ms	0	1	0.00
V2	chip_sw_sleep_pin_wake	chip_sw_sleep_pin_wake	2.972m	3.370ms	1	1	100.00
V2	chip_sw_sleep_pin_retention	chip_sw_sleep_pin_retention	2.762m	3.287ms	1	1	100.00
V2	chip_sw_tap_strap_sampling	chip_tap_straps_dev	1.851m	2.180ms	1	1	100.00
		chip_tap_straps_testunlock0	2.370m	3.477ms	1	1	100.00
		chip_tap_straps_rma	7.568m	8.682ms	1	1	100.00
		chip_tap_straps_prod	7.248m	7.530ms	1	1	100.00
V2	chip_sw_pattgen_ios	chip_sw_pattgen_ios	2.039m	3.092ms	1	1	100.00
V2	chip_sw_sleep_pwm_pulses	chip_sw_sleep_pwm_pulses	13.854m	9.201ms	1	1	100.00
V2	chip_sw_data_integrity	chip_sw_data_integrity_escalation	6.587m	5.211ms	1	1	100.00
V2	chip_sw_instruction_integrity	chip_sw_data_integrity_escalation	6.587m	5.211ms	1	1	100.00
V2	chip_sw_ast_clk_outputs	chip_sw_ast_clk_outputs	10.940m	9.021ms	1	1	100.00
V2	chip_sw_ast_clk_rst_inputs	chip_sw_ast_clk_rst_inputs	28.254m	17.530ms	0	1	0.00
V2	chip_sw_ast_sys_clk_jitter	chip_sw_flash_ctrl_ops_jitter_en	6.505m	4.734ms	1	1	100.00
		chip_sw_flash_ctrl_access_jitter_en	9.234m	5.317ms	1	1	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en	55.822m	19.149ms	1	1	100.00
		chip_sw_aes_enc_jitter_en	1.949m	2.377ms	1	1	100.00
		chip_sw_edn_entropy_reqs_jitter	7.880m	4.963ms	1	1	100.00
		chip_sw_hmac_enc_jitter_en	2.257m	2.420ms	1	1	100.00
		chip_sw_keymgr_key_derivation_jitter_en	10.277m	6.101ms	1	1	100.00
		chip_sw_kmac_mode_kmac_jitter_en	2.762m	2.491ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	5.609m	5.614ms	1	1	100.00
		chip_sw_clkmgr_jitter	2.011m	2.770ms	1	1	100.00
V2	chip_sw_ast_usb_clk_calib	chip_sw_usb_ast_clk_calib	2.723m	2.589ms	1	1	100.00
V2	chip_sw_sensor_ctrl_ast_alerts	chip_sw_sensor_ctrl_alert	8.157m	6.757ms	1	1	100.00
		chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	4.991m	4.637ms	1	1	100.00
V2	chip_sw_sensor_ctrl_ast_status	chip_sw_sensor_ctrl_status	1.853m	2.894ms	1	1	100.00
V2	chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	4.991m	4.637ms	1	1	100.00
V2	chip_sw_smoketest	chip_sw_flash_scrambling_smoketest	2.592m	3.336ms	1	1	100.00
		chip_sw_aes_smoketest	2.866m	3.221ms	1	1	100.00
		chip_sw_aon_timer_smoketest	2.808m	2.523ms	1	1	100.00
		chip_sw_clkmgr_smoketest	2.319m	3.375ms	1	1	100.00
		chip_sw_csrng_smoketest	1.684m	2.142ms	1	1	100.00
		chip_sw_entropy_src_smoketest	11.940m	5.866ms	1	1	100.00
		chip_sw_gpio_smoketest	2.344m	2.908ms	1	1	100.00
		chip_sw_hmac_smoketest	2.636m	2.963ms	1	1	100.00
		chip_sw_kmac_smoketest	2.468m	3.099ms	1	1	100.00
		chip_sw_otbn_smoketest	9.100m	5.502ms	1	1	100.00
		chip_sw_pwrmgr_smoketest	4.974m	6.725ms	1	1	100.00
		chip_sw_pwrmgr_usbdev_smoketest	3.340m	5.818ms	1	1	100.00
		chip_sw_rv_plic_smoketest	2.446m	3.282ms	1	1	100.00
		chip_sw_rv_timer_smoketest	2.397m	2.234ms	1	1	100.00
		chip_sw_rstmgr_smoketest	2.904m	3.140ms	1	1	100.00
		chip_sw_sram_ctrl_smoketest	1.954m	2.590ms	1	1	100.00
		chip_sw_uart_smoketest	2.444m	2.878ms	1	1	100.00
V2	chip_sw_otp_smoketest	chip_sw_otp_ctrl_smoketest	3.008m	2.662ms	1	1	100.00
V2	chip_sw_rom_functests	rom_keymgr_functest	4.356m	4.105ms	1	1	100.00
V2	chip_sw_boot	chip_sw_uart_tx_rx_bootstrap	2.204h	60.638ms	1	1	100.00
V2	chip_sw_secure_boot	rom_e2e_smoke	43.723m	14.782ms	1	1	100.00
V2	chip_sw_rom_raw_unlock	rom_raw_unlock	2.769m	5.841ms	1	1	100.00
V2	chip_sw_power_idle_load	chip_sw_power_idle_load	3.166m	2.980ms	0	1	0.00
V2	chip_sw_power_sleep_load	chip_sw_power_sleep_load	3.934m	3.046ms	0	1	0.00
V2	chip_sw_exit_test_unlocked_bootstrap	chip_sw_exit_test_unlocked_bootstrap	1.961h	53.409ms	1	1	100.00
V2	chip_sw_inject_scramble_seed	chip_sw_inject_scramble_seed	2.090h	55.338ms	1	1	100.00
V2	tl_d_oob_addr_access	chip_tl_errors	47.300s	2.107ms	0	1	0.00
V2	tl_d_illegal_access	chip_tl_errors	47.300s	2.107ms	0	1	0.00
V2	tl_d_outstanding_access	chip_csr_aliasing	1.242h	36.387ms	1	1	100.00
		chip_same_csr_outstanding	21.404m	17.685ms	1	1	100.00
		chip_csr_hw_reset	2.109m	4.144ms	1	1	100.00
		chip_csr_rw	3.468m	3.978ms	1	1	100.00
V2	tl_d_partial_access	chip_csr_aliasing	1.242h	36.387ms	1	1	100.00
		chip_same_csr_outstanding	21.404m	17.685ms	1	1	100.00
		chip_csr_hw_reset	2.109m	4.144ms	1	1	100.00
		chip_csr_rw	3.468m	3.978ms	1	1	100.00
V2	xbar_base_random_sequence	xbar_random	19.940s	869.337us	1	1	100.00
V2	xbar_random_delay	xbar_smoke_zero_delays	4.280s	43.270us	1	1	100.00
		xbar_smoke_large_delays	57.470s	9.215ms	1	1	100.00
		xbar_smoke_slow_rsp	42.800s	4.975ms	1	1	100.00
		xbar_random_zero_delays	16.620s	300.870us	1	1	100.00
		xbar_random_large_delays	3.776m	37.847ms	1	1	100.00
		xbar_random_slow_rsp	5.123m	35.962ms	1	1	100.00
V2	xbar_unmapped_address	xbar_unmapped_addr	10.170s	222.090us	1	1	100.00
		xbar_error_and_unmapped_addr	7.100s	174.109us	1	1	100.00
V2	xbar_error_cases	xbar_error_random	24.130s	846.441us	1	1	100.00
		xbar_error_and_unmapped_addr	7.100s	174.109us	1	1	100.00
V2	xbar_all_access_same_device	xbar_access_same_device	1.368m	2.937ms	1	1	100.00
		xbar_access_same_device_slow_rsp	5.347m	39.159ms	1	1	100.00
V2	xbar_all_hosts_use_same_source_id	xbar_same_source	20.350s	666.776us	1	1	100.00
V2	xbar_stress_all	xbar_stress_all	1.568m	4.780ms	1	1	100.00
		xbar_stress_all_with_error	28.700s	666.267us	1	1	100.00
V2	xbar_stress_with_reset	xbar_stress_all_with_rand_reset	1.495m	257.758us	1	1	100.00
		xbar_stress_all_with_reset_error	7.610s	9.944us	1	1	100.00
V2	rom_e2e_smoke	rom_e2e_smoke	43.723m	14.782ms	1	1	100.00
V2	rom_e2e_shutdown_output	rom_e2e_shutdown_output	41.105m	33.437ms	0	1	0.00
V2	rom_e2e_shutdown_exception_c	rom_e2e_shutdown_exception_c	42.111m	16.886ms	1	1	100.00
V2	rom_e2e_boot_policy_valid	rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0	33.032m	10.952ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_dev	42.632m	14.920ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod	43.054m	16.069ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod_end	44.590m	16.485ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_rma	42.290m	16.072ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0	22.110s	10.120us	0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_dev	21.730s	10.300us	0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod	17.450s	10.220us	0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod_end	17.150s	10.160us	0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_rma	18.530s	10.260us	0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0	17.330s	10.320us	0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_dev	28.600s	10.400us	0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod	17.810s	10.400us	0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod_end	21.010s	10.160us	0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_rma	16.660s	10.320us	0	1	0.00
V2	rom_e2e_sigverify_always	rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0	20.030s	10.280us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_dev	16.900s	10.180us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod	18.370s	10.140us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod_end	16.940s	10.300us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_rma	17.390s	10.220us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0	22.340s	10.320us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_dev	21.420s	10.340us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod	19.170s	10.320us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod_end	23.040s	10.120us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_rma	17.660s	10.140us	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0	17.290s	10.200us	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_dev	17.590s	10.320us	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod	16.530s	10.320us	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod_end	17.420s	10.400us	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_rma	16.670s	10.160us	0	1	0.00
V2	rom_e2e_asm_init	rom_e2e_asm_init_test_unlocked0	33.416m	13.519ms	0	1	0.00
		rom_e2e_asm_init_dev	42.918m	17.415ms	1	1	100.00
		rom_e2e_asm_init_prod	41.806m	16.548ms	1	1	100.00
		rom_e2e_asm_init_prod_end	40.821m	15.698ms	1	1	100.00
		rom_e2e_asm_init_rma	40.989m	14.759ms	1	1	100.00
V2	rom_e2e_keymgr_init	rom_e2e_keymgr_init_rom_ext_meas	41.332m	15.030ms	1	1	100.00
		rom_e2e_keymgr_init_rom_ext_no_meas	37.990m	14.365ms	1	1	100.00
		rom_e2e_keymgr_init_rom_ext_invalid_meas	40.371m	15.400ms	1	1	100.00
V2	rom_e2e_static_critical	rom_e2e_static_critical	42.550m	15.639ms	1	1	100.00
V2	chip_sw_adc_ctrl_debug_cable_irq	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	50.216m	34.931ms	0	1	0.00
V2	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	50.216m	34.931ms	0	1	0.00
V2	chip_sw_aes_enc	chip_sw_aes_enc	2.909m	2.840ms	1	1	100.00
		chip_sw_aes_enc_jitter_en	1.949m	2.377ms	1	1	100.00
V2	chip_sw_aes_entropy	chip_sw_aes_entropy	1.848m	2.367ms	1	1	100.00
V2	chip_sw_aes_idle	chip_sw_aes_idle	2.861m	3.280ms	1	1	100.00
V2	chip_sw_aes_sideload	chip_sw_keymgr_sideload_aes	11.311m	6.861ms	1	1	100.00
V2	chip_sw_alert_handler_alerts	chip_sw_alert_test	2.542m	2.895ms	0	1	0.00
V2	chip_sw_alert_handler_escalations	chip_sw_alert_handler_escalation	6.405m	5.619ms	1	1	100.00
V2	chip_sw_all_escalation_resets	chip_sw_all_escalation_resets	6.736m	6.097ms	1	1	100.00
V2	chip_sw_alert_handler_irqs	chip_plic_all_irqs_0	9.953m	5.979ms	1	1	100.00
		chip_plic_all_irqs_10	4.200m	3.624ms	1	1	100.00
		chip_plic_all_irqs_20	6.451m	4.084ms	1	1	100.00
V2	chip_sw_alert_handler_entropy	chip_sw_alert_handler_entropy	2.934m	2.861ms	1	1	100.00
V2	chip_sw_alert_handler_crashdump	chip_sw_rstmgr_alert_info	18.294m	12.532ms	1	1	100.00
V2	chip_sw_alert_handler_ping_timeout	chip_sw_alert_handler_ping_timeout	5.391m	5.033ms	1	1	100.00
V2	chip_sw_alert_handler_lpg_sleep_mode_alerts	chip_sw_alert_handler_lpg_sleep_mode_alerts	2.434m	3.325ms	0	1	0.00
V2	chip_sw_alert_handler_lpg_sleep_mode_pings	chip_sw_alert_handler_lpg_sleep_mode_pings			0	1	0.00
V2	chip_sw_alert_handler_lpg_clock_off	chip_sw_alert_handler_lpg_clkoff	8.058m	4.808ms	1	1	100.00
V2	chip_sw_alert_handler_lpg_reset_toggle	chip_sw_alert_handler_lpg_reset_toggle	17.950m	8.120ms	1	1	100.00
V2	chip_sw_alert_handler_ping_ok	chip_sw_alert_handler_ping_ok	14.194m	8.263ms	1	1	100.00
V2	chip_sw_alert_handler_reverse_ping_in_deep_sleep	chip_sw_alert_handler_reverse_ping_in_deep_sleep	2.143h	255.089ms	1	1	100.00
V2	chip_sw_aon_timer_wakeup_irq	chip_sw_aon_timer_irq	3.548m	3.602ms	1	1	100.00
V2	chip_sw_aon_timer_sleep_wakeup	chip_sw_pwrmgr_smoketest	4.974m	6.725ms	1	1	100.00
V2	chip_sw_aon_timer_wdog_bark_irq	chip_sw_aon_timer_irq	3.548m	3.602ms	1	1	100.00
V2	chip_sw_aon_timer_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	8.131m	7.632ms	1	1	100.00
V2	chip_sw_aon_timer_sleep_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	8.131m	7.632ms	1	1	100.00
V2	chip_sw_aon_timer_sleep_wdog_sleep_pause	chip_sw_aon_timer_sleep_wdog_sleep_pause	3.137m	7.316ms	1	1	100.00
V2	chip_sw_aon_timer_wdog_lc_escalate	chip_sw_aon_timer_wdog_lc_escalate	5.466m	5.411ms	1	1	100.00
V2	chip_sw_clkmgr_idle_trans	chip_sw_otbn_randomness	10.222m	6.197ms	1	1	100.00
		chip_sw_aes_idle	2.861m	3.280ms	1	1	100.00
		chip_sw_hmac_enc_idle	2.154m	2.674ms	1	1	100.00
		chip_sw_kmac_idle	2.613m	2.531ms	1	1	100.00
V2	chip_sw_clkmgr_off_trans	chip_sw_clkmgr_off_aes_trans	3.924m	4.016ms	1	1	100.00
		chip_sw_clkmgr_off_hmac_trans	5.055m	5.347ms	1	1	100.00
		chip_sw_clkmgr_off_kmac_trans	3.852m	3.833ms	1	1	100.00
		chip_sw_clkmgr_off_otbn_trans	3.534m	4.103ms	1	1	100.00
V2	chip_sw_clkmgr_off_peri	chip_sw_clkmgr_off_peri	11.464m	8.811ms	1	1	100.00
V2	chip_sw_clkmgr_div	chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	5.740m	3.978ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	6.191m	4.766ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	5.575m	4.036ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	6.361m	4.521ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	5.656m	3.795ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	6.670m	4.869ms	1	1	100.00
		chip_sw_ast_clk_outputs	10.940m	9.021ms	1	1	100.00
V2	chip_sw_clkmgr_external_clk_src_for_lc	chip_sw_clkmgr_external_clk_src_for_lc	5.011m	6.752ms	1	1	100.00
V2	chip_sw_clkmgr_external_clk_src_for_sw	chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	5.575m	4.036ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	6.361m	4.521ms	1	1	100.00
V2	chip_sw_clkmgr_jitter	chip_sw_flash_ctrl_ops_jitter_en	6.505m	4.734ms	1	1	100.00
		chip_sw_flash_ctrl_access_jitter_en	9.234m	5.317ms	1	1	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en	55.822m	19.149ms	1	1	100.00
		chip_sw_aes_enc_jitter_en	1.949m	2.377ms	1	1	100.00
		chip_sw_edn_entropy_reqs_jitter	7.880m	4.963ms	1	1	100.00
		chip_sw_hmac_enc_jitter_en	2.257m	2.420ms	1	1	100.00
		chip_sw_keymgr_key_derivation_jitter_en	10.277m	6.101ms	1	1	100.00
		chip_sw_kmac_mode_kmac_jitter_en	2.762m	2.491ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	5.609m	5.614ms	1	1	100.00
		chip_sw_clkmgr_jitter	2.011m	2.770ms	1	1	100.00
V2	chip_sw_clkmgr_extended_range	chip_sw_clkmgr_jitter_reduced_freq	2.003m	2.423ms	1	1	100.00
		chip_sw_flash_ctrl_ops_jitter_en_reduced_freq	5.974m	5.226ms	1	1	100.00
		chip_sw_flash_ctrl_access_jitter_en_reduced_freq	11.108m	6.563ms	1	1	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq	53.182m	24.435ms	1	1	100.00
		chip_sw_aes_enc_jitter_en_reduced_freq	3.095m	3.483ms	1	1	100.00
		chip_sw_hmac_enc_jitter_en_reduced_freq	2.620m	2.935ms	1	1	100.00
		chip_sw_keymgr_key_derivation_jitter_en_reduced_freq	16.296m	10.494ms	1	1	100.00
		chip_sw_kmac_mode_kmac_jitter_en_reduced_freq	2.390m	3.253ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq	4.726m	4.501ms	1	1	100.00
		chip_sw_flash_init_reduced_freq	23.764m	23.496ms	1	1	100.00
		chip_sw_csrng_edn_concurrency_reduced_freq	48.029m	27.449ms	1	1	100.00
V2	chip_sw_clkmgr_deep_sleep_frequency	chip_sw_ast_clk_outputs	10.940m	9.021ms	1	1	100.00
V2	chip_sw_clkmgr_sleep_frequency	chip_sw_clkmgr_sleep_frequency	5.513m	4.428ms	1	1	100.00
V2	chip_sw_clkmgr_reset_frequency	chip_sw_clkmgr_reset_frequency	4.018m	3.411ms	1	1	100.00
V2	chip_sw_clkmgr_escalation_reset	chip_sw_all_escalation_resets	6.736m	6.097ms	1	1	100.00
V2	chip_sw_clkmgr_alert_handler_clock_enables	chip_sw_alert_handler_lpg_clkoff	8.058m	4.808ms	1	1	100.00
V2	chip_sw_csrng_edn_cmd	chip_sw_entropy_src_csrng	16.120m	6.892ms	1	1	100.00
V2	chip_sw_csrng_fuse_en_sw_app_read	chip_sw_csrng_fuse_en_sw_app_read_test	4.213m	5.036ms	1	1	100.00
V2	chip_sw_csrng_lc_hw_debug_en	chip_sw_csrng_lc_hw_debug_en_test	6.884m	7.357ms	1	1	100.00
V2	chip_sw_csrng_known_answer_tests	chip_sw_csrng_kat_test	2.290m	2.622ms	1	1	100.00
V2	chip_sw_edn_entropy_reqs	chip_sw_csrng_edn_concurrency	1.009h	21.650ms	1	1	100.00
		chip_sw_entropy_src_ast_rng_req	2.653m	2.864ms	1	1	100.00
		chip_sw_edn_entropy_reqs	12.592m	6.047ms	1	1	100.00
V2	chip_sw_entropy_src_ast_rng_req	chip_sw_entropy_src_ast_rng_req	2.653m	2.864ms	1	1	100.00
V2	chip_sw_entropy_src_csrng	chip_sw_entropy_src_csrng	16.120m	6.892ms	1	1	100.00
V2	chip_sw_entropy_src_known_answer_tests	chip_sw_entropy_src_kat_test	1.693m	2.107ms	1	1	100.00
V2	chip_sw_flash_init	chip_sw_flash_init	26.845m	25.032ms	1	1	100.00
V2	chip_sw_flash_host_access	chip_sw_flash_ctrl_access	9.492m	5.733ms	1	1	100.00
		chip_sw_flash_ctrl_access_jitter_en	9.234m	5.317ms	1	1	100.00
V2	chip_sw_flash_ctrl_ops	chip_sw_flash_ctrl_ops	6.051m	4.161ms	1	1	100.00
		chip_sw_flash_ctrl_ops_jitter_en	6.505m	4.734ms	1	1	100.00
V2	chip_sw_flash_rma_unlocked	chip_sw_flash_rma_unlocked	54.624m	43.299ms	1	1	100.00
V2	chip_sw_flash_scramble	chip_sw_flash_init	26.845m	25.032ms	1	1	100.00
V2	chip_sw_flash_idle_low_power	chip_sw_flash_ctrl_idle_low_power	3.363m	2.630ms	1	1	100.00
V2	chip_sw_flash_keymgr_seeds	chip_sw_keymgr_key_derivation	29.346m	13.603ms	1	1	100.00
V2	chip_sw_flash_lc_creator_seed_sw_rw_en	chip_sw_flash_ctrl_lc_rw_en	3.942m	3.766ms	1	1	100.00
V2	chip_sw_flash_creator_seed_wipe_on_rma	chip_sw_flash_rma_unlocked	54.624m	43.299ms	1	1	100.00
V2	chip_sw_flash_lc_owner_seed_sw_rw_en	chip_sw_flash_ctrl_lc_rw_en	3.942m	3.766ms	1	1	100.00
V2	chip_sw_flash_lc_iso_part_sw_rd_en	chip_sw_flash_ctrl_lc_rw_en	3.942m	3.766ms	1	1	100.00
V2	chip_sw_flash_lc_iso_part_sw_wr_en	chip_sw_flash_ctrl_lc_rw_en	3.942m	3.766ms	1	1	100.00
V2	chip_sw_flash_lc_seed_hw_rd_en	chip_sw_flash_ctrl_lc_rw_en	3.942m	3.766ms	1	1	100.00
V2	chip_sw_flash_lc_escalate_en	chip_sw_all_escalation_resets	6.736m	6.097ms	1	1	100.00
V2	chip_sw_flash_prim_tl_access	chip_prim_tl_access	3.345m	9.073ms	1	1	100.00
V2	chip_sw_flash_ctrl_clock_freqs	chip_sw_flash_ctrl_clock_freqs	8.704m	5.024ms	1	1	100.00
V2	chip_sw_flash_ctrl_escalation_reset	chip_sw_flash_crash_alert	7.100m	6.375ms	1	1	100.00
V2	chip_sw_flash_ctrl_write_clear	chip_sw_flash_crash_alert	7.100m	6.375ms	1	1	100.00
V2	chip_sw_hmac_enc	chip_sw_hmac_enc	2.414m	3.101ms	1	1	100.00
		chip_sw_hmac_enc_jitter_en	2.257m	2.420ms	1	1	100.00
V2	chip_sw_hmac_idle	chip_sw_hmac_enc_idle	2.154m	2.674ms	1	1	100.00
V2	chip_sw_hmac_all_configurations	chip_sw_hmac_oneshot	2.140m	2.357ms	0	1	0.00
V2	chip_sw_hmac_multistream_mode	chip_sw_hmac_multistream	5.436m	3.653ms	1	1	100.00
V2	chip_sw_i2c_host_tx_rx	chip_sw_i2c_host_tx_rx	7.418m	5.397ms	1	1	100.00
		chip_sw_i2c_host_tx_rx_idx1	6.566m	4.967ms	1	1	100.00
		chip_sw_i2c_host_tx_rx_idx2	6.388m	4.571ms	1	1	100.00
V2	chip_sw_i2c_device_tx_rx	chip_sw_i2c_device_tx_rx	3.887m	3.489ms	1	1	100.00
V2	chip_sw_keymgr_key_derivation	chip_sw_keymgr_key_derivation	29.346m	13.603ms	1	1	100.00
		chip_sw_keymgr_key_derivation_jitter_en	10.277m	6.101ms	1	1	100.00
V2	chip_sw_keymgr_sideload_kmac	chip_sw_keymgr_sideload_kmac	16.147m	7.815ms	1	1	100.00
V2	chip_sw_keymgr_sideload_aes	chip_sw_keymgr_sideload_aes	11.311m	6.861ms	1	1	100.00
V2	chip_sw_keymgr_sideload_otbn	chip_sw_keymgr_sideload_otbn	40.749m	13.619ms	1	1	100.00
V2	chip_sw_kmac_enc	chip_sw_kmac_mode_cshake	1.710m	2.974ms	1	1	100.00
		chip_sw_kmac_mode_kmac	2.965m	3.079ms	1	1	100.00
		chip_sw_kmac_mode_kmac_jitter_en	2.762m	2.491ms	1	1	100.00
V2	chip_sw_kmac_app_keymgr	chip_sw_keymgr_key_derivation	29.346m	13.603ms	1	1	100.00
V2	chip_sw_kmac_app_lc	chip_sw_lc_ctrl_transition	12.098m	13.234ms	1	1	100.00
V2	chip_sw_kmac_app_rom	chip_sw_kmac_app_rom	2.378m	2.808ms	1	1	100.00
V2	chip_sw_kmac_entropy	chip_sw_kmac_entropy	25.578m	10.691ms	1	1	100.00
V2	chip_sw_kmac_idle	chip_sw_kmac_idle	2.613m	2.531ms	1	1	100.00
V2	chip_sw_lc_ctrl_alert_handler_escalation	chip_sw_alert_handler_escalation	6.405m	5.619ms	1	1	100.00
V2	chip_sw_lc_ctrl_jtag_access	chip_tap_straps_dev	1.851m	2.180ms	1	1	100.00
		chip_tap_straps_rma	7.568m	8.682ms	1	1	100.00
		chip_tap_straps_prod	7.248m	7.530ms	1	1	100.00
V2	chip_sw_lc_ctrl_otp_hw_cfg0	chip_sw_lc_ctrl_otp_hw_cfg0	3.139m	3.233ms	1	1	100.00
V2	chip_sw_lc_ctrl_init	chip_sw_lc_ctrl_transition	12.098m	13.234ms	1	1	100.00
V2	chip_sw_lc_ctrl_transitions	chip_sw_lc_ctrl_transition	12.098m	13.234ms	1	1	100.00
V2	chip_sw_lc_ctrl_kmac_req	chip_sw_lc_ctrl_transition	12.098m	13.234ms	1	1	100.00
V2	chip_sw_lc_ctrl_key_div	chip_sw_keymgr_key_derivation_prod	24.068m	10.897ms	1	1	100.00
V2	chip_sw_lc_ctrl_broadcast	chip_sw_flash_ctrl_lc_rw_en	3.942m	3.766ms	1	1	100.00
		chip_sw_flash_rma_unlocked	54.624m	43.299ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_test_unlocked0	4.033m	3.091ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_dev	9.460m	6.569ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_prod	7.541m	5.214ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_rma	8.423m	7.506ms	1	1	100.00
		chip_sw_lc_ctrl_transition	12.098m	13.234ms	1	1	100.00
		chip_sw_keymgr_key_derivation	29.346m	13.603ms	1	1	100.00
		chip_sw_rom_ctrl_integrity_check	5.791m	9.212ms	1	1	100.00
		chip_sw_sram_ctrl_execution_main	7.612m	9.189ms	1	1	100.00
		chip_prim_tl_access	3.345m	9.073ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_lc	5.011m	6.752ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	5.740m	3.978ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	6.191m	4.766ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	5.575m	4.036ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	6.361m	4.521ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	5.656m	3.795ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	6.670m	4.869ms	1	1	100.00
		chip_tap_straps_dev	1.851m	2.180ms	1	1	100.00
		chip_tap_straps_rma	7.568m	8.682ms	1	1	100.00
		chip_tap_straps_prod	7.248m	7.530ms	1	1	100.00
		chip_rv_dm_lc_disabled	2.397m	5.317ms	0	1	0.00
V2	chip_lc_scrap	chip_sw_lc_ctrl_rma_to_scrap	2.731m	3.724ms	1	1	100.00
		chip_sw_lc_ctrl_raw_to_scrap	1.347m	3.881ms	1	1	100.00
		chip_sw_lc_ctrl_test_locked0_to_scrap	1.527m	3.276ms	1	1	100.00
		chip_sw_lc_ctrl_rand_to_scrap	2.698m	3.621ms	1	1	100.00
V2	chip_lc_test_locked	chip_sw_lc_walkthrough_testunlocks	21.101m	23.029ms	1	1	100.00
		chip_rv_dm_lc_disabled	2.397m	5.317ms	0	1	0.00
V2	chip_sw_lc_walkthrough	chip_sw_lc_walkthrough_dev	1.012h	46.693ms	1	1	100.00
		chip_sw_lc_walkthrough_prod	1.094h	46.292ms	1	1	100.00
		chip_sw_lc_walkthrough_prodend	10.388m	10.067ms	1	1	100.00
		chip_sw_lc_walkthrough_rma	1.086h	48.531ms	1	1	100.00
		chip_sw_lc_walkthrough_testunlocks	21.101m	23.029ms	1	1	100.00
V2	chip_sw_lc_ctrl_volatile_raw_unlock	chip_sw_lc_ctrl_volatile_raw_unlock	1.208m	2.126ms	1	1	100.00
		chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz	1.045m	2.207ms	1	1	100.00
		rom_volatile_raw_unlock	1.084m	2.985ms	1	1	100.00
V2	chip_sw_otbn_op	chip_sw_otbn_ecdsa_op_irq	57.696m	17.188ms	1	1	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en	55.822m	19.149ms	1	1	100.00
V2	chip_sw_otbn_rnd_entropy	chip_sw_otbn_randomness	10.222m	6.197ms	1	1	100.00
V2	chip_sw_otbn_urnd_entropy	chip_sw_otbn_randomness	10.222m	6.197ms	1	1	100.00
V2	chip_sw_otbn_idle	chip_sw_otbn_randomness	10.222m	6.197ms	1	1	100.00
V2	chip_sw_otbn_mem_scramble	chip_sw_otbn_mem_scramble	5.870m	4.036ms	1	1	100.00
V2	chip_otp_ctrl_init	chip_sw_lc_ctrl_transition	12.098m	13.234ms	1	1	100.00
V2	chip_sw_otp_ctrl_keys	chip_sw_flash_init	26.845m	25.032ms	1	1	100.00
		chip_sw_otbn_mem_scramble	5.870m	4.036ms	1	1	100.00
		chip_sw_keymgr_key_derivation	29.346m	13.603ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access	6.464m	5.138ms	1	1	100.00
		chip_sw_rv_core_ibex_icache_invalidate	2.478m	3.175ms	1	1	100.00
V2	chip_sw_otp_ctrl_entropy	chip_sw_flash_init	26.845m	25.032ms	1	1	100.00
		chip_sw_otbn_mem_scramble	5.870m	4.036ms	1	1	100.00
		chip_sw_keymgr_key_derivation	29.346m	13.603ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access	6.464m	5.138ms	1	1	100.00
		chip_sw_rv_core_ibex_icache_invalidate	2.478m	3.175ms	1	1	100.00
V2	chip_sw_otp_ctrl_program	chip_sw_lc_ctrl_transition	12.098m	13.234ms	1	1	100.00
V2	chip_sw_otp_ctrl_program_error	chip_sw_lc_ctrl_program_error	5.548m	4.378ms	1	1	100.00
V2	chip_sw_otp_ctrl_hw_cfg0	chip_sw_lc_ctrl_otp_hw_cfg0	3.139m	3.233ms	1	1	100.00
V2	chip_sw_otp_ctrl_lc_signals	chip_sw_otp_ctrl_lc_signals_test_unlocked0	4.033m	3.091ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_dev	9.460m	6.569ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_prod	7.541m	5.214ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_rma	8.423m	7.506ms	1	1	100.00
		chip_sw_lc_ctrl_transition	12.098m	13.234ms	1	1	100.00
		chip_prim_tl_access	3.345m	9.073ms	1	1	100.00
V2	chip_sw_otp_prim_tl_access	chip_prim_tl_access	3.345m	9.073ms	1	1	100.00
V2	chip_sw_otp_ctrl_dai_lock	chip_sw_otp_ctrl_dai_lock	16.662m	7.977ms	1	1	100.00
V2	chip_sw_pwrmgr_external_full_reset	chip_sw_pwrmgr_full_aon_reset	5.277m	6.335ms	1	1	100.00
V2	chip_sw_pwrmgr_random_sleep_all_wake_ups	chip_sw_pwrmgr_random_sleep_all_wake_ups	21.774m	25.650ms	1	1	100.00
V2	chip_sw_pwrmgr_normal_sleep_all_wake_ups	chip_sw_pwrmgr_normal_sleep_all_wake_ups	4.126m	7.584ms	1	1	100.00
V2	chip_sw_pwrmgr_deep_sleep_por_reset	chip_sw_pwrmgr_deep_sleep_por_reset	5.513m	7.252ms	1	1	100.00
V2	chip_sw_pwrmgr_normal_sleep_por_reset	chip_sw_pwrmgr_normal_sleep_por_reset	7.063m	7.175ms	1	1	100.00
V2	chip_sw_pwrmgr_deep_sleep_all_wake_ups	chip_sw_pwrmgr_deep_sleep_all_wake_ups	13.694m	20.432ms	1	1	100.00
V2	chip_sw_pwrmgr_deep_sleep_all_reset_reqs	chip_sw_pwrmgr_deep_sleep_all_reset_reqs	13.733m	16.084ms	1	1	100.00
		chip_sw_aon_timer_wdog_bite_reset	8.131m	7.632ms	1	1	100.00
V2	chip_sw_pwrmgr_normal_sleep_all_reset_reqs	chip_sw_pwrmgr_normal_sleep_all_reset_reqs	11.756m	11.027ms	1	1	100.00
V2	chip_sw_pwrmgr_wdog_reset	chip_sw_pwrmgr_wdog_reset	5.421m	4.344ms	1	1	100.00
V2	chip_sw_pwrmgr_aon_power_glitch_reset	chip_sw_pwrmgr_full_aon_reset	5.277m	6.335ms	1	1	100.00
V2	chip_sw_pwrmgr_main_power_glitch_reset	chip_sw_pwrmgr_main_power_glitch_reset	5.870m	5.796ms	1	1	100.00
V2	chip_sw_pwrmgr_random_sleep_power_glitch_reset	chip_sw_pwrmgr_random_sleep_power_glitch_reset	43.408m	40.900ms	1	1	100.00
V2	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	4.159m	6.735ms	1	1	100.00
V2	chip_sw_pwrmgr_sleep_power_glitch_reset	chip_sw_pwrmgr_sleep_power_glitch_reset	4.846m	4.189ms	1	1	100.00
V2	chip_sw_pwrmgr_random_sleep_all_reset_reqs	chip_sw_pwrmgr_random_sleep_all_reset_reqs	27.398m	26.533ms	1	1	100.00
V2	chip_sw_pwrmgr_sysrst_ctrl_reset	chip_sw_pwrmgr_sysrst_ctrl_reset	11.588m	7.872ms	1	1	100.00
		chip_sw_pwrmgr_all_reset_reqs	14.960m	9.176ms	1	1	100.00
V2	chip_sw_pwrmgr_b2b_sleep_reset_req	chip_sw_pwrmgr_b2b_sleep_reset_req	33.517m	28.604ms	1	1	100.00
V2	chip_sw_pwrmgr_sleep_disabled	chip_sw_pwrmgr_sleep_disabled	2.473m	3.254ms	1	1	100.00
V2	chip_sw_pwrmgr_escalation_reset	chip_sw_all_escalation_resets	6.736m	6.097ms	1	1	100.00
V2	chip_sw_rom_access	chip_sw_rom_ctrl_integrity_check	5.791m	9.212ms	1	1	100.00
V2	chip_sw_rom_ctrl_integrity_check	chip_sw_rom_ctrl_integrity_check	5.791m	9.212ms	1	1	100.00
V2	chip_sw_rstmgr_non_sys_reset_info	chip_sw_pwrmgr_all_reset_reqs	14.960m	9.176ms	1	1	100.00
		chip_sw_pwrmgr_random_sleep_all_reset_reqs	27.398m	26.533ms	1	1	100.00
		chip_sw_pwrmgr_wdog_reset	5.421m	4.344ms	1	1	100.00
		chip_sw_pwrmgr_smoketest	4.974m	6.725ms	1	1	100.00
V2	chip_sw_rstmgr_sys_reset_info	chip_rv_dm_ndm_reset_req	3.757m	3.624ms	1	1	100.00
V2	chip_sw_rstmgr_cpu_info	chip_sw_rstmgr_cpu_info	3.566m	3.348ms	0	1	0.00
V2	chip_sw_rstmgr_sw_req_reset	chip_sw_rstmgr_sw_req	3.945m	3.904ms	1	1	100.00
V2	chip_sw_rstmgr_alert_info	chip_sw_rstmgr_alert_info	18.294m	12.532ms	1	1	100.00
V2	chip_sw_rstmgr_sw_rst	chip_sw_rstmgr_sw_rst	2.699m	3.620ms	1	1	100.00
V2	chip_sw_rstmgr_escalation_reset	chip_sw_all_escalation_resets	6.736m	6.097ms	1	1	100.00
V2	chip_sw_rstmgr_alert_handler_reset_enables	chip_sw_alert_handler_lpg_reset_toggle	17.950m	8.120ms	1	1	100.00
V2	chip_sw_nmi_irq	chip_sw_rv_core_ibex_nmi_irq	6.838m	4.417ms	1	1	100.00
V2	chip_sw_rv_core_ibex_rnd	chip_sw_rv_core_ibex_rnd	8.592m	5.052ms	1	1	100.00
V2	chip_sw_rv_core_ibex_address_translation	chip_sw_rv_core_ibex_address_translation	2.654m	2.973ms	1	1	100.00
V2	chip_sw_rv_core_ibex_icache_scrambled_access	chip_sw_rv_core_ibex_icache_invalidate	2.478m	3.175ms	1	1	100.00
V2	chip_sw_rv_core_ibex_fault_dump	chip_sw_rstmgr_cpu_info	3.566m	3.348ms	0	1	0.00
V2	chip_sw_rv_core_ibex_double_fault	chip_sw_rstmgr_cpu_info	3.566m	3.348ms	0	1	0.00
V2	chip_jtag_csr_rw	chip_jtag_csr_rw	13.900m	11.851ms	1	1	100.00
V2	chip_jtag_mem_access	chip_jtag_mem_access	14.242m	13.106ms	1	1	100.00
V2	chip_rv_dm_ndm_reset_req	chip_rv_dm_ndm_reset_req	3.757m	3.624ms	1	1	100.00
V2	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	4.447m	4.368ms	1	1	100.00
V2	chip_rv_dm_access_after_wakeup	chip_sw_rv_dm_access_after_wakeup	4.055m	5.404ms	1	1	100.00
V2	chip_sw_rv_dm_jtag_tap_sel	chip_tap_straps_rma	7.568m	8.682ms	1	1	100.00
V2	chip_rv_dm_lc_disabled	chip_rv_dm_lc_disabled	2.397m	5.317ms	0	1	0.00
V2	chip_sw_plic_all_irqs	chip_plic_all_irqs_0	9.953m	5.979ms	1	1	100.00
		chip_plic_all_irqs_10	4.200m	3.624ms	1	1	100.00
		chip_plic_all_irqs_20	6.451m	4.084ms	1	1	100.00
V2	chip_sw_plic_sw_irq	chip_sw_plic_sw_irq	1.686m	2.847ms	1	1	100.00
V2	chip_sw_timer	chip_sw_rv_timer_irq	1.941m	3.225ms	1	1	100.00
V2	chip_sw_spi_device_flash_mode	rom_e2e_smoke	43.723m	14.782ms	1	1	100.00
V2	chip_sw_spi_device_pass_through	chip_sw_spi_device_pass_through	7.583m	6.781ms	1	1	100.00
V2	chip_sw_spi_device_pass_through_collision	chip_sw_spi_device_pass_through_collision	2.203m	2.761ms	0	1	0.00
V2	chip_sw_spi_device_tpm	chip_sw_spi_device_tpm	2.746m	2.830ms	1	1	100.00
V2	chip_sw_spi_host_tx_rx	chip_sw_spi_host_tx_rx	2.290m	2.701ms	1	1	100.00
V2	chip_sw_sram_scrambled_access	chip_sw_sram_ctrl_scrambled_access	6.464m	5.138ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	5.609m	5.614ms	1	1	100.00
V2	chip_sw_sleep_sram_ret_contents	chip_sw_sleep_sram_ret_contents_no_scramble	5.805m	8.215ms	1	1	100.00
		chip_sw_sleep_sram_ret_contents_scramble	8.232m	8.575ms	1	1	100.00
V2	chip_sw_sram_execution	chip_sw_sram_ctrl_execution_main	7.612m	9.189ms	1	1	100.00
V2	chip_sw_sram_lc_escalation	chip_sw_all_escalation_resets	6.736m	6.097ms	1	1	100.00
		chip_sw_data_integrity_escalation	6.587m	5.211ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_reset	chip_sw_pwrmgr_sysrst_ctrl_reset	11.588m	7.872ms	1	1	100.00
		chip_sw_sysrst_ctrl_reset	19.139m	21.887ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_inputs	chip_sw_sysrst_ctrl_inputs	2.274m	2.997ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_outputs	chip_sw_sysrst_ctrl_outputs	2.831m	3.495ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_in_irq	chip_sw_sysrst_ctrl_in_irq	5.353m	4.806ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_sleep_wakeup	chip_sw_sysrst_ctrl_reset	19.139m	21.887ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_sleep_reset	chip_sw_sysrst_ctrl_reset	19.139m	21.887ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_ec_rst_l	chip_sw_sysrst_ctrl_ec_rst_l	43.196m	21.017ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_flash_wp_l	chip_sw_sysrst_ctrl_ec_rst_l	43.196m	21.017ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_ulp_z3_wakeup	chip_sw_sysrst_ctrl_ulp_z3_wakeup	3.276m	5.196ms	1	1	100.00
		chip_sw_adc_ctrl_sleep_debug_cable_wakeup	50.216m	34.931ms	0	1	0.00
V2	chip_sw_usbdev_vbus	chip_sw_usbdev_vbus	2.039m	2.830ms	1	1	100.00
V2	chip_sw_usbdev_pullup	chip_sw_usbdev_pullup	2.905m	3.345ms	1	1	100.00
V2	chip_sw_usbdev_aon_pullup	chip_sw_usbdev_aon_pullup	4.521m	3.916ms	1	1	100.00
V2	chip_sw_usbdev_setup_rx	chip_sw_usbdev_setuprx	4.309m	3.702ms	1	1	100.00
V2	chip_sw_usbdev_config_host	chip_sw_usbdev_config_host	17.493m	8.624ms	1	1	100.00
V2	chip_sw_usbdev_pincfg	chip_sw_usbdev_pincfg	1.467h	32.149ms	1	1	100.00
V2	chip_sw_usbdev_tx_rx	chip_sw_usbdev_dpi	28.822m	11.560ms	1	1	100.00
V2	chip_sw_usbdev_toggle_restore	chip_sw_usbdev_toggle_restore	2.457m	3.031ms	1	1	100.00
V2		TOTAL			235	275	85.45
V2S	chip_sw_aes_masking_off	chip_sw_aes_masking_off	2.715m	2.962ms	1	1	100.00
V2S	chip_sw_rv_core_ibex_lockstep_glitch	chip_sw_rv_core_ibex_lockstep_glitch	1.618m	2.290ms	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	chip_sw_coremark	chip_sw_coremark	2.606h	72.428ms	1	1	100.00
V3	chip_sw_power_max_load	chip_sw_power_virus	6.665m	3.391ms	0	1	0.00
V3	rom_e2e_debug	rom_e2e_jtag_debug_test_unlocked0	18.970m	11.191ms	1	1	100.00
		rom_e2e_jtag_debug_dev	18.759m	10.674ms	1	1	100.00
		rom_e2e_jtag_debug_rma	19.162m	10.437ms	1	1	100.00
V3	rom_e2e_jtag_inject	rom_e2e_jtag_inject_test_unlocked0	3.360m	5.948ms	1	1	100.00
		rom_e2e_jtag_inject_dev	3.168m	4.669ms	1	1	100.00
		rom_e2e_jtag_inject_rma	2.906m	3.882ms	1	1	100.00
V3	rom_e2e_self_hash	rom_e2e_self_hash	12.225s		0	1	0.00
V3	chip_sw_clkmgr_jitter_cycle_measurements	chip_sw_clkmgr_jitter_frequency	8.882m	5.152ms	1	1	100.00
V3	chip_sw_edn_boot_mode	chip_sw_edn_boot_mode	4.896m	2.793ms	1	1	100.00
V3	chip_sw_edn_auto_mode	chip_sw_edn_auto_mode	19.394m	7.170ms	1	1	100.00
V3	chip_sw_edn_sw_mode	chip_sw_edn_sw_mode	15.387m	6.959ms	1	1	100.00
V3	chip_sw_edn_kat	chip_sw_edn_kat	3.699m	2.571ms	1	1	100.00
V3	chip_sw_flash_memory_protection	chip_sw_flash_ctrl_mem_protection	10.286m	5.801ms	1	1	100.00
V3	chip_sw_otp_ctrl_vendor_test_csr_access	chip_sw_otp_ctrl_vendor_test_csr_access	59.950s	2.085ms	1	1	100.00
V3	chip_sw_otp_ctrl_escalation	chip_sw_otp_ctrl_escalation	6.996m	5.686ms	1	1	100.00
V3	chip_sw_sensor_ctrl_deep_sleep_wake_up	chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up	5.312m	5.235ms	1	1	100.00
V3	chip_sw_pwrmgr_usb_clk_disabled_when_active	chip_sw_pwrmgr_usb_clk_disabled_when_active	4.740m	4.316ms	1	1	100.00
V3	chip_sw_all_resets	chip_sw_pwrmgr_all_reset_reqs	14.960m	9.176ms	1	1	100.00
V3	chip_rv_dm_perform_debug	rom_e2e_jtag_debug_test_unlocked0	18.970m	11.191ms	1	1	100.00
		rom_e2e_jtag_debug_dev	18.759m	10.674ms	1	1	100.00
		rom_e2e_jtag_debug_rma	19.162m	10.437ms	1	1	100.00
V3	chip_sw_rv_dm_access_after_hw_reset	chip_sw_rv_dm_access_after_escalation_reset	6.163m	5.038ms	1	1	100.00
V3	chip_sw_plic_alerts	chip_sw_all_escalation_resets	6.736m	6.097ms	1	1	100.00
V3	tick_configuration	chip_sw_rv_timer_systick_test	1.550h	38.121ms	1	1	100.00
V3	counter_wrap	chip_sw_rv_timer_systick_test	1.550h	38.121ms	1	1	100.00
V3	chip_sw_spi_device_output_when_disabled_or_sleeping	chip_sw_spi_device_pinmux_sleep_retention	2.433m	2.897ms	1	1	100.00
V3	chip_sw_uart_watermarks	chip_sw_uart_tx_rx	6.073m	4.283ms	1	1	100.00
V3	chip_sw_usbdev_stream	chip_sw_usbdev_stream	55.346m	19.380ms	1	1	100.00
V3		TOTAL			21	23	91.30
	Unmapped tests	chip_sival_flash_info_access	2.986m	2.846ms	1	1	100.00
		chip_sw_rstmgr_rst_cnsty_escalation	5.754m	5.315ms	1	1	100.00
		chip_sw_otp_ctrl_rot_auth_config	33.941m	35.114ms	0	1	0.00
		chip_sw_otp_ctrl_ecc_error_vendor_test	2.440m	2.328ms	1	1	100.00
		chip_sw_otp_ctrl_descrambling	3.013m	2.970ms	1	1	100.00
		chip_sw_pwrmgr_lowpower_cancel	3.756m	3.815ms	1	1	100.00
		chip_sw_pwrmgr_sleep_wake_5_bug	15.168s		0	1	0.00
		chip_sw_flash_ctrl_write_clear	2.720m	2.936ms	1	1	100.00
		TOTAL			281	326	86.20

Failure Buckets

UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_*.signed.*.scr.vmem could not be opened for r mode has 11 failures:
- Test rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0 has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0.100591519352803556623710388531978470796834411908942635832609065412238502255136
    Line 484, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0/latest/run.log
```
  UVM_FATAL @  10.320001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.320001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_bad_b_good_dev has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_bad_b_good_dev.89893112425902517059614764142220500638476544188230460937411606242697965730065
    Line 470, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_dev/latest/run.log
```
  UVM_FATAL @  10.400001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.400001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_bad_b_good_prod has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_bad_b_good_prod.60711131552082411625745073197939579942201712954376810222378876584012525518011
    Line 502, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod/latest/run.log
```
  UVM_FATAL @  10.400001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.400001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_bad_b_good_prod_end has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_bad_b_good_prod_end.51279015905182439384997739176938106731659562201182745397430057770350110341073
    Line 503, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod_end/latest/run.log
```
  UVM_FATAL @  10.160001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.160001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_bad_b_good_rma has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_bad_b_good_rma.53050090943244603641819257381214383477982178863328936693671226850886881299516
    Line 503, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_rma/latest/run.log
```
  UVM_FATAL @  10.320001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.320001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- ... and 6 more tests.
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_*.signed.*.scr.vmem could not be opened for r mode has 5 failures:
- Test rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0 has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0.49714229630590049834887885737887016445632344775275005594391979022175143892173
    Line 513, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0/latest/run.log
```
  UVM_FATAL @  10.120001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.120001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_good_b_bad_dev has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_good_b_bad_dev.39454118674551884246962046245720482243097806330471627735384770033771940884551
    Line 510, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_dev/latest/run.log
```
  UVM_FATAL @  10.300001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.300001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_good_b_bad_prod has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_good_b_bad_prod.37070169627797667476703468819427980391500590744976996057721812255109557594575
    Line 501, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod/latest/run.log
```
  UVM_FATAL @  10.220001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.220001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_good_b_bad_prod_end has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_good_b_bad_prod_end.3319647837952502809116783620151516574532138993164480206249177342523572082741
    Line 498, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod_end/latest/run.log
```
  UVM_FATAL @  10.160001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.160001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_good_b_bad_rma has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_good_b_bad_rma.113644789420321193569233146441976599139512116870962666256399358427123636091748
    Line 474, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_rma/latest/run.log
```
  UVM_FATAL @  10.260001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.260001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_*.signed.*.scr.vmem could not be opened for r mode has 3 failures:
- Test rom_e2e_sigverify_always_a_nothing_b_bad_prod has 1 failures.
  - 0.rom_e2e_sigverify_always_a_nothing_b_bad_prod.11846890331294366219546585077227616308634515238584595557722825162440806153209
    Line 472, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod/latest/run.log
```
  UVM_FATAL @  10.320001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.320001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_sigverify_always_a_nothing_b_bad_prod_end has 1 failures.
  - 0.rom_e2e_sigverify_always_a_nothing_b_bad_prod_end.17449254231655916315633261019453246586919107433229429169552529045282205695859
    Line 514, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod_end/latest/run.log
```
  UVM_FATAL @  10.400001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.400001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_sigverify_always_a_nothing_b_bad_rma has 1 failures.
  - 0.rom_e2e_sigverify_always_a_nothing_b_bad_rma.53790551379162581806101337890391412506734083015108280228104723436626905280542
    Line 496, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_rma/latest/run.log
```
  UVM_FATAL @  10.160001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.160001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

Job returned non-zero exit code has 2 failures:

Test chip_sw_pwrmgr_sleep_wake_5_bug has 1 failures.

0.chip_sw_pwrmgr_sleep_wake_5_bug.23260012109049509122198190293693479549350029592857941747777856626538317465419
Log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_pwrmgr_sleep_wake_5_bug/latest/run.log

  Computing main repo mapping:
  Loading:
  Loading: 0 packages loaded
  WARNING: Target pattern parsing failed.
  ERROR: Skipping '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD
  ERROR: no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD
  INFO: Elapsed time: 2.047s
  INFO: 0 processes.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

Test rom_e2e_self_hash has 1 failures.

0.rom_e2e_self_hash.22421310441136954225291964784081681992271508393556647297853991163129275342496
Log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_self_hash/latest/run.log

  Computing main repo mapping:
  Loading:
  Loading: 0 packages loaded
  WARNING: Target pattern parsing failed.
  ERROR: Skipping '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD
  ERROR: no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD
  INFO: Elapsed time: 0.169s
  INFO: 0 processes.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

Offending '(pend_req[h2d.a_source].pend == *)' has 2 failures:

Test rom_e2e_shutdown_output has 1 failures.

0.rom_e2e_shutdown_output.70650688158958953221531468334157283158829580970582784370003890362760839251595
Line 466, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_shutdown_output/latest/run.log

      Offending '(pend_req[h2d.a_source].pend == 0)'
  "src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 284: tb.dut.top_earlgrey.u_rstmgr_aon.tlul_assert_device.gen_device.gen_h2d.pendingReqPerSrc_M: started at 20563098462ps failed at 20563098462ps
      Offending '(pend_req[h2d.a_source].pend == 0)'
  "src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 284: tb.dut.top_earlgrey.u_rstmgr_aon.tlul_assert_device.gen_device.gen_h2d.pendingReqPerSrc_M: started at 20563259790ps failed at 20563259790ps
      Offending '(pend_req[h2d.a_source].pend == 0)'

Test rom_e2e_asm_init_test_unlocked0 has 1 failures.

0.rom_e2e_asm_init_test_unlocked0.30855889295095978551192299804832770683997173503323839777295266023840466432791
Line 447, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_asm_init_test_unlocked0/latest/run.log

      Offending '(pend_req[h2d.a_source].pend == 0)'
  "src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 284: tb.dut.top_earlgrey.u_rstmgr_aon.tlul_assert_device.gen_device.gen_h2d.pendingReqPerSrc_M: started at 3043524309ps failed at 3043524309ps
      Offending '(pend_req[h2d.a_source].pend == 0)'
  "src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 284: tb.dut.top_earlgrey.u_rstmgr_aon.tlul_assert_device.gen_device.gen_h2d.pendingReqPerSrc_M: started at 3043711461ps failed at 3043711461ps
      Offending '(pend_req[h2d.a_source].pend == 0)'

UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_test_key_*.signed.*.scr.vmem could not be opened for r mode has 2 failures:
- Test rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0 has 1 failures.
  - 0.rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0.28523778206985683798930652226960512582352372536287874811609513605923295479619
    Line 521, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0/latest/run.log
```
  UVM_FATAL @  10.280001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_test_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.280001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0 has 1 failures.
  - 0.rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0.92330117232065183808702595553994740404222135304279232912698397277625103918315
    Line 489, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0/latest/run.log
```
  UVM_FATAL @  10.320001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_test_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.320001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_dev_key_*.signed.*.scr.vmem could not be opened for r mode has 2 failures:
- Test rom_e2e_sigverify_always_a_bad_b_bad_dev has 1 failures.
  - 0.rom_e2e_sigverify_always_a_bad_b_bad_dev.67604092560918163512186572332174187852671337630971076336111746506014512110249
    Line 511, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_bad_dev/latest/run.log
```
  UVM_FATAL @  10.180001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_dev_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.180001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_sigverify_always_a_bad_b_nothing_dev has 1 failures.
  - 0.rom_e2e_sigverify_always_a_bad_b_nothing_dev.41010488762846812776679298997798198461817026648925991939912762368126100595050
    Line 485, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_nothing_dev/latest/run.log
```
  UVM_FATAL @  10.340001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_dev_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.340001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (chip_sw_sleep_pin_mio_dio_val_vseq.sv:92) [chip_sw_sleep_pin_mio_dio_val_vseq] Check failed cfg.chip_vif.mios_if.pins[i] === exp (* [*] vs *xz [z]) for MIO[*] has 1 failures:
- Test chip_sw_sleep_pin_mio_dio_val has 1 failures.
  - 0.chip_sw_sleep_pin_mio_dio_val.62735237514219992071076585342587832798108784284187007131918433288274369013794
    Line 563, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_sleep_pin_mio_dio_val/latest/run.log
```
  UVM_ERROR @ 3065.945000 us: (chip_sw_sleep_pin_mio_dio_val_vseq.sv:92) [uvm_test_top.env.virtual_sequencer.chip_sw_sleep_pin_mio_dio_val_vseq] Check failed cfg.chip_vif.mios_if.pins[i] === exp (0x0 [0] vs 0xz [z]) for MIO[30]
  UVM_INFO @ 3065.945000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:379)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty has 1 failures:
- Test chip_sw_spi_device_pass_through_collision has 1 failures.
  - 0.chip_sw_spi_device_pass_through_collision.72978917076797926910185051043804877062395301279021083333823607987876986175724
    Line 400, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_spi_device_pass_through_collision/latest/run.log
```
  UVM_ERROR @ 2761.198704 us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:379)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty
  UVM_INFO @ 2761.198704 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [otp_ctrl_rot_auth_config_test_sim_dv(sw/device/tests/otp_ctrl_rot_auth_config_test.c:22)] CHECK-STATUS-fail: @@@:* = ErrorError has 1 failures:
- Test chip_sw_otp_ctrl_rot_auth_config has 1 failures.
  - 0.chip_sw_otp_ctrl_rot_auth_config.60982223604439044179354436777474960060630018208786719188832620922114291957770
    Line 437, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_otp_ctrl_rot_auth_config/latest/run.log
```
  UVM_ERROR @ 35113.668750 us: (sw_logger_if.sv:526) [otp_ctrl_rot_auth_config_test_sim_dv(sw/device/tests/otp_ctrl_rot_auth_config_test.c:22)] CHECK-STATUS-fail: @@@:0 = ErrorError
  UVM_INFO @ 35113.668750 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@96716) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_sw_rstmgr_cpu_info has 1 failures.

0.chip_sw_rstmgr_cpu_info.8899800149416797161085006813364686553541953260917218628359844370820406815758
Line 418, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_rstmgr_cpu_info/latest/run.log

  UVM_ERROR @ 3347.631032 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (1 [0x1] vs 0 [0x0]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@96716) { a_addr: 'h8  a_data: 'h0  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h1  a_opcode: 'h0  a_user: 'h259aa  d_param: 'h0  d_source: 'h1  d_data: 'h0  d_size: 'h2  d_opcode: 'h0  d_error: 'h1  d_sink: 'h0  d_user: 'h1f2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 3347.631032 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (chip_sw_base_vseq.sv:317) virtual_sequencer [chip_sw_adc_ctrl_sleep_debug_cable_wakeup_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = * ns has 1 failures:
- Test chip_sw_adc_ctrl_sleep_debug_cable_wakeup has 1 failures.
  - 0.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.66909188332386739163465799958559371593945088584932137192316708349600608516015
    Line 419, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_adc_ctrl_sleep_debug_cable_wakeup/latest/run.log
```
  UVM_ERROR @ 34930.537651 us: (chip_sw_base_vseq.sv:317) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_adc_ctrl_sleep_debug_cable_wakeup_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = 18000000 ns

  UVM_INFO @ 34930.537651 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_test_sim_dv(hw/top_earlgrey/sw/autogen/tests/alert_test.c:307)] CHECK-fail: Expect alert *! has 1 failures:
- Test chip_sw_alert_test has 1 failures.
  - 0.chip_sw_alert_test.114561956510697913972495769734063528457247150342650389256385004826243168615864
    Line 391, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_alert_test/latest/run.log
```
  UVM_ERROR @ 2894.625160 us: (sw_logger_if.sv:526) [alert_test_sim_dv(hw/top_earlgrey/sw/autogen/tests/alert_test.c:307)] CHECK-fail: Expect alert 42!
  UVM_INFO @ 2894.625160 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0) has 1 failures:
- Test chip_sw_alert_handler_lpg_sleep_mode_alerts has 1 failures.
  - 0.chip_sw_alert_handler_lpg_sleep_mode_alerts.73222965262884495197603340172862769099183508924050914020036658041803107903139
    Line 391, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log
```
  UVM_ERROR @ 3324.539558 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
  UVM_INFO @ 3324.539558 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Job timed out after * minutes has 1 failures:
- Test chip_sw_alert_handler_lpg_sleep_mode_pings has 1 failures.
  - 0.chip_sw_alert_handler_lpg_sleep_mode_pings.73418050042110487123194946517431602657958960397430390162885971823524115363951
    Log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_alert_handler_lpg_sleep_mode_pings/latest/run.log
```
  Job timed out after 240 minutes
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [hmac_functest_sim_dv(sw/device/tests/crypto/hmac_functest.c:79)] Finished test run_test_vector: *. has 1 failures:
- Test chip_sw_hmac_oneshot has 1 failures.
  - 0.chip_sw_hmac_oneshot.106085189543003579989192250383706453716402205880537572619677904684020203217871
    Line 395, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_hmac_oneshot/latest/run.log
```
  UVM_ERROR @ 2356.577466 us: (sw_logger_if.sv:526) [hmac_functest_sim_dv(sw/device/tests/crypto/hmac_functest.c:79)] Finished test run_test_vector: 8000534a.
  UVM_INFO @ 2356.577466 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@40110) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_tl_errors has 1 failures.

0.chip_tl_errors.60308214742398292825567928625477310063855324505751740663275694380165134726329
Line 214, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_tl_errors/latest/run.log

  UVM_ERROR @ 2106.822440 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@40110) { a_addr: 'h1063c  a_data: 'hf4e6dc61  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'he  a_opcode: 'h4  a_user: 'h1ba90  d_param: 'h0  d_source: 'he  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 2106.822440 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (cip_base_vseq.sv:642) [chip_rv_dm_lc_disabled_vseq] Check failed masked_data == exp_data (* [*] vs * [*]) addr * read out mismatch has 1 failures:
- Test chip_rv_dm_lc_disabled has 1 failures.
  - 0.chip_rv_dm_lc_disabled.81430727017996290998843489685979219223227598125778629805270548284050306980945
    Line 229, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_rv_dm_lc_disabled/latest/run.log
```
  UVM_ERROR @ 5316.643566 us: (cip_base_vseq.sv:642) [uvm_test_top.env.virtual_sequencer.chip_rv_dm_lc_disabled_vseq] Check failed masked_data == exp_data (0 [0x0] vs 4294967295 [0xffffffff]) addr 0x10794 read out mismatch
  UVM_INFO @ 5316.643566 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (chip_sw_power_idle_load_vseq.sv:91) virtual_sequencer [chip_sw_power_idle_load_vseq] PWMCH* : pkt* Clock period is wrong. rcv : * exp : * has 1 failures:
- Test chip_sw_power_idle_load has 1 failures.
  - 0.chip_sw_power_idle_load.30365415710930770114035615944661963869318691793372820019964804833994795531931
    Line 395, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_power_idle_load/latest/run.log
```
  UVM_ERROR @ 2979.933000 us: (chip_sw_power_idle_load_vseq.sv:91) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_power_idle_load_vseq] PWMCH5 : pkt3 Clock period is wrong.  rcv : 2  exp : 32
  UVM_INFO @ 2979.933000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (chip_sw_power_sleep_load_vseq.sv:114) virtual_sequencer [chip_sw_power_sleep_load_vseq] PWMCH* : pkt* Clock period is wrong. rcv : * exp : * has 1 failures:
- Test chip_sw_power_sleep_load has 1 failures.
  - 0.chip_sw_power_sleep_load.74736740087953432451023107608417288681952710346979382556747914000069439156357
    Line 404, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_power_sleep_load/latest/run.log
```
  UVM_ERROR @ 3045.804000 us: (chip_sw_power_sleep_load_vseq.sv:114) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_power_sleep_load_vseq] PWMCH5 : pkt3 Clock period is wrong.  rcv : 2  exp : 32
  UVM_INFO @ 3045.804000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [ast_clk_rst_inputs_sim_dv(sw/device/tests/sim_dv/ast_clk_rst_inputs.c:147)] CHECK-fail: Recov alert not correctly observed in alert handler has 1 failures:
- Test chip_sw_ast_clk_rst_inputs has 1 failures.
  - 0.chip_sw_ast_clk_rst_inputs.57962052310490317751610649027559870488244046913957890735351960727595046043908
    Line 423, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_ast_clk_rst_inputs/latest/run.log
```
  UVM_ERROR @ 17529.818786 us: (sw_logger_if.sv:526) [ast_clk_rst_inputs_sim_dv(sw/device/tests/sim_dv/ast_clk_rst_inputs.c:147)] CHECK-fail: Recov alert not correctly observed in alert handler
  UVM_INFO @ 17529.818786 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (chip_sw_power_virus_vseq.sv:196) [chip_sw_power_virus_vseq] Check failed csrng_acmd_q >= * (* [*] vs * [*]) has 1 failures:
- Test chip_sw_power_virus has 1 failures.
  - 0.chip_sw_power_virus.73027306872595455919557495069554748731633794991433842310103712395141456528456
    Line 444, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_power_virus/latest/run.log
```
  UVM_ERROR @ 3390.731008 us: (chip_sw_power_virus_vseq.sv:196) [uvm_test_top.env.virtual_sequencer.chip_sw_power_virus_vseq] Check failed csrng_acmd_q >= 2 (1 [0x1] vs 2 [0x2])
  UVM_INFO @ 3390.731008 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_test_key_*.signed.*.scr.vmem could not be opened for r mode has 1 failures:
- Test rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0 has 1 failures.
  - 0.rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0.21219417852247740702140176708673873505825153932268609021533563045549436702440
    Line 454, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0/latest/run.log
```
  UVM_FATAL @  10.200001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_test_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.200001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_dev_key_*.signed.*.scr.vmem could not be opened for r mode has 1 failures:
- Test rom_e2e_sigverify_always_a_nothing_b_bad_dev has 1 failures.
  - 0.rom_e2e_sigverify_always_a_nothing_b_bad_dev.14175090584540213582698520757253754409591828317235872003262537259426510063080
    Line 454, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_dev/latest/run.log
```
  UVM_FATAL @  10.320001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_dev_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.320001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@32152) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_csr_mem_rw_with_rand_reset has 1 failures.

0.chip_csr_mem_rw_with_rand_reset.111631337646037451566223116618950554488615459493529873857988620119415209749472
Line 221, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_csr_mem_rw_with_rand_reset/latest/run.log

  UVM_ERROR @ 2256.531144 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@32152) { a_addr: 'h10698  a_data: 'h17121deb  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h23  a_opcode: 'h4  a_user: 'h19e6b  d_param: 'h0  d_source: 'h23  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 2256.531144 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---