ADC_CTRL Simulation Results

Thursday October 09 2025 19:22:42 UTC

GitHub Revision: 677ee3d

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	adc_ctrl_smoke	6.050s	6.020ms	1	1	100.00
V1	csr_hw_reset	adc_ctrl_csr_hw_reset	2.760s	1.158ms	1	1	100.00
V1	csr_rw	adc_ctrl_csr_rw	1.230s	344.553us	1	1	100.00
V1	csr_bit_bash	adc_ctrl_csr_bit_bash	26.870s	27.846ms	1	1	100.00
V1	csr_aliasing	adc_ctrl_csr_aliasing	2.710s	724.899us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	adc_ctrl_csr_mem_rw_with_rand_reset	1.460s	578.860us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	adc_ctrl_csr_rw	1.230s	344.553us	1	1	100.00
		adc_ctrl_csr_aliasing	2.710s	724.899us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	filters_polled	adc_ctrl_filters_polled	2.559m	163.399ms	1	1	100.00
V2	filters_polled_fixed	adc_ctrl_filters_polled_fixed	2.406m	162.253ms	1	1	100.00
V2	filters_interrupt	adc_ctrl_filters_interrupt	4.368m	163.892ms	1	1	100.00
V2	filters_interrupt_fixed	adc_ctrl_filters_interrupt_fixed	1.033m	169.218ms	1	1	100.00
V2	filters_wakeup	adc_ctrl_filters_wakeup	2.450m	176.242ms	1	1	100.00
V2	filters_wakeup_fixed	adc_ctrl_filters_wakeup_fixed	3.108m	198.667ms	1	1	100.00
V2	filters_both	adc_ctrl_filters_both	1.445m	329.678ms	1	1	100.00
V2	clock_gating	adc_ctrl_clock_gating	1.070s	2.406ms	0	1	0.00
V2	poweron_counter	adc_ctrl_poweron_counter	15.100s	4.958ms	1	1	100.00
V2	lowpower_counter	adc_ctrl_lowpower_counter	43.590s	24.791ms	1	1	100.00
V2	fsm_reset	adc_ctrl_fsm_reset	1.026m	121.764ms	1	1	100.00
V2	stress_all	adc_ctrl_stress_all	27.510s	169.100ms	1	1	100.00
V2	alert_test	adc_ctrl_alert_test	0.920s	453.435us	1	1	100.00
V2	intr_test	adc_ctrl_intr_test	1.310s	358.268us	1	1	100.00
V2	tl_d_oob_addr_access	adc_ctrl_tl_errors	2.530s	416.299us	1	1	100.00
V2	tl_d_illegal_access	adc_ctrl_tl_errors	2.530s	416.299us	1	1	100.00
V2	tl_d_outstanding_access	adc_ctrl_csr_hw_reset	2.760s	1.158ms	1	1	100.00
		adc_ctrl_csr_rw	1.230s	344.553us	1	1	100.00
		adc_ctrl_csr_aliasing	2.710s	724.899us	1	1	100.00
		adc_ctrl_same_csr_outstanding	1.640s	4.624ms	1	1	100.00
V2	tl_d_partial_access	adc_ctrl_csr_hw_reset	2.760s	1.158ms	1	1	100.00
		adc_ctrl_csr_rw	1.230s	344.553us	1	1	100.00
		adc_ctrl_csr_aliasing	2.710s	724.899us	1	1	100.00
		adc_ctrl_same_csr_outstanding	1.640s	4.624ms	1	1	100.00
V2		TOTAL			15	16	93.75
V2S	tl_intg_err	adc_ctrl_sec_cm	7.970s	7.789ms	1	1	100.00
		adc_ctrl_tl_intg_err	4.710s	4.327ms	1	1	100.00
V2S	sec_cm_bus_integrity	adc_ctrl_tl_intg_err	4.710s	4.327ms	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	stress_all_with_rand_reset	adc_ctrl_stress_all_with_rand_reset	12.570s	62.444ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			24	25	96.00

Failure Buckets

• UVM_ERROR (cip_base_scoreboard.sv:255) scoreboard [scoreboard] alert fatal_fault has unexpected timeout error has 1 failures:
  • Test adc_ctrl_clock_gating has 1 failures.

    • 0.adc_ctrl_clock_gating.64200310947515273885520830003113587522470017771855892680461223886587661147175
      Line 148, in log /nightly/current_run/scratch/master/adc_ctrl-sim-vcs/0.adc_ctrl_clock_gating/latest/run.log

        UVM_ERROR @ 2406265393 ps: (cip_base_scoreboard.sv:255) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault has unexpected timeout error
        UVM_INFO @ 2406265393 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---