EDN Simulation Results

Thursday October 09 2025 19:22:42 UTC

GitHub Revision: 677ee3d

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	edn_smoke	0.960s	27.952us	1	1	100.00
V1	csr_hw_reset	edn_csr_hw_reset	0.840s	25.941us	1	1	100.00
V1	csr_rw	edn_csr_rw	0.840s	36.255us	1	1	100.00
V1	csr_bit_bash	edn_csr_bit_bash	1.650s	223.629us	1	1	100.00
V1	csr_aliasing	edn_csr_aliasing	1.080s	20.677us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	edn_csr_mem_rw_with_rand_reset	0.920s	71.345us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	edn_csr_rw	0.840s	36.255us	1	1	100.00
		edn_csr_aliasing	1.080s	20.677us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	firmware	edn_genbits	2.050s	48.965us	1	1	100.00
V2	csrng_commands	edn_genbits	2.050s	48.965us	1	1	100.00
V2	genbits	edn_genbits	2.050s	48.965us	1	1	100.00
V2	interrupts	edn_intr	0.850s	27.556us	1	1	100.00
V2	alerts	edn_alert	1.110s	26.205us	1	1	100.00
V2	errs	edn_err	1.190s	19.615us	1	1	100.00
V2	disable	edn_disable	0.960s	26.120us	1	1	100.00
		edn_disable_auto_req_mode	1.100s	133.568us	1	1	100.00
V2	stress_all	edn_stress_all	2.700s	166.548us	1	1	100.00
V2	intr_test	edn_intr_test	0.770s	17.805us	1	1	100.00
V2	alert_test	edn_alert_test	0.900s	20.676us	1	1	100.00
V2	tl_d_oob_addr_access	edn_tl_errors	1.760s	129.833us	1	1	100.00
V2	tl_d_illegal_access	edn_tl_errors	1.760s	129.833us	1	1	100.00
V2	tl_d_outstanding_access	edn_csr_hw_reset	0.840s	25.941us	1	1	100.00
		edn_csr_rw	0.840s	36.255us	1	1	100.00
		edn_csr_aliasing	1.080s	20.677us	1	1	100.00
		edn_same_csr_outstanding	0.980s	47.675us	1	1	100.00
V2	tl_d_partial_access	edn_csr_hw_reset	0.840s	25.941us	1	1	100.00
		edn_csr_rw	0.840s	36.255us	1	1	100.00
		edn_csr_aliasing	1.080s	20.677us	1	1	100.00
		edn_same_csr_outstanding	0.980s	47.675us	1	1	100.00
V2		TOTAL			11	11	100.00
V2S	tl_intg_err	edn_sec_cm	5.450s	491.064us	1	1	100.00
		edn_tl_intg_err	1.230s	41.160us	1	1	100.00
V2S	sec_cm_config_regwen	edn_regwen	0.860s	31.340us	1	1	100.00
V2S	sec_cm_config_mubi	edn_alert	1.110s	26.205us	1	1	100.00
V2S	sec_cm_main_sm_fsm_sparse	edn_sec_cm	5.450s	491.064us	1	1	100.00
V2S	sec_cm_ack_sm_fsm_sparse	edn_sec_cm	5.450s	491.064us	1	1	100.00
V2S	sec_cm_fifo_ctr_redun	edn_sec_cm	5.450s	491.064us	1	1	100.00
V2S	sec_cm_ctr_redun	edn_sec_cm	5.450s	491.064us	1	1	100.00
V2S	sec_cm_main_sm_ctr_local_esc	edn_alert	1.110s	26.205us	1	1	100.00
		edn_sec_cm	5.450s	491.064us	1	1	100.00
V2S	sec_cm_cs_rdata_bus_consistency	edn_alert	1.110s	26.205us	1	1	100.00
V2S	sec_cm_tile_link_bus_integrity	edn_tl_intg_err	1.230s	41.160us	1	1	100.00
V2S		TOTAL			3	3	100.00
V3	stress_all_with_rand_reset	edn_stress_all_with_rand_reset	1.292m	8.193ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			21	21	100.00