HMAC Simulation Results

Thursday October 09 2025 19:22:42 UTC

GitHub Revision: 677ee3d

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke hmac_smoke 8.000s 861.583us 1 1 100.00
V1 csr_hw_reset hmac_csr_hw_reset 0.870s 21.774us 1 1 100.00
V1 csr_rw hmac_csr_rw 0.700s 64.127us 1 1 100.00
V1 csr_bit_bash hmac_csr_bit_bash 4.480s 548.221us 1 1 100.00
V1 csr_aliasing hmac_csr_aliasing 2.520s 218.416us 1 1 100.00
V1 csr_mem_rw_with_rand_reset hmac_csr_mem_rw_with_rand_reset 0.920s 58.282us 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr hmac_csr_rw 0.700s 64.127us 1 1 100.00
hmac_csr_aliasing 2.520s 218.416us 1 1 100.00
V1 TOTAL 6 6 100.00
V2 long_msg hmac_long_msg 14.500s 716.078us 1 1 100.00
V2 back_pressure hmac_back_pressure 1.107m 1.410ms 1 1 100.00
V2 test_vectors hmac_test_sha256_vectors 8.100s 166.247us 1 1 100.00
hmac_test_sha384_vectors 7.706m 30.508ms 1 1 100.00
hmac_test_sha512_vectors 7.476m 14.255ms 1 1 100.00
hmac_test_hmac256_vectors 6.130s 204.690us 1 1 100.00
hmac_test_hmac384_vectors 8.690s 238.224us 1 1 100.00
hmac_test_hmac512_vectors 13.100s 750.592us 1 1 100.00
V2 burst_wr hmac_burst_wr 10.070s 4.498ms 1 1 100.00
V2 datapath_stress hmac_datapath_stress 7.909m 14.798ms 1 1 100.00
V2 error hmac_error 27.800s 2.037ms 1 1 100.00
V2 wipe_secret hmac_wipe_secret 8.470s 413.122us 1 1 100.00
V2 save_and_restore hmac_smoke 8.000s 861.583us 1 1 100.00
hmac_long_msg 14.500s 716.078us 1 1 100.00
hmac_back_pressure 1.107m 1.410ms 1 1 100.00
hmac_datapath_stress 7.909m 14.798ms 1 1 100.00
hmac_burst_wr 10.070s 4.498ms 1 1 100.00
hmac_stress_all 23.657m 12.938ms 1 1 100.00
V2 fifo_empty_status_interrupt hmac_smoke 8.000s 861.583us 1 1 100.00
hmac_long_msg 14.500s 716.078us 1 1 100.00
hmac_back_pressure 1.107m 1.410ms 1 1 100.00
hmac_datapath_stress 7.909m 14.798ms 1 1 100.00
hmac_wipe_secret 8.470s 413.122us 1 1 100.00
hmac_test_sha256_vectors 8.100s 166.247us 1 1 100.00
hmac_test_sha384_vectors 7.706m 30.508ms 1 1 100.00
hmac_test_sha512_vectors 7.476m 14.255ms 1 1 100.00
hmac_test_hmac256_vectors 6.130s 204.690us 1 1 100.00
hmac_test_hmac384_vectors 8.690s 238.224us 1 1 100.00
hmac_test_hmac512_vectors 13.100s 750.592us 1 1 100.00
V2 wide_digest_configurable_key_length hmac_smoke 8.000s 861.583us 1 1 100.00
hmac_long_msg 14.500s 716.078us 1 1 100.00
hmac_back_pressure 1.107m 1.410ms 1 1 100.00
hmac_datapath_stress 7.909m 14.798ms 1 1 100.00
hmac_burst_wr 10.070s 4.498ms 1 1 100.00
hmac_error 27.800s 2.037ms 1 1 100.00
hmac_wipe_secret 8.470s 413.122us 1 1 100.00
hmac_test_sha256_vectors 8.100s 166.247us 1 1 100.00
hmac_test_sha384_vectors 7.706m 30.508ms 1 1 100.00
hmac_test_sha512_vectors 7.476m 14.255ms 1 1 100.00
hmac_test_hmac256_vectors 6.130s 204.690us 1 1 100.00
hmac_test_hmac384_vectors 8.690s 238.224us 1 1 100.00
hmac_test_hmac512_vectors 13.100s 750.592us 1 1 100.00
hmac_stress_all 23.657m 12.938ms 1 1 100.00
V2 stress_all hmac_stress_all 23.657m 12.938ms 1 1 100.00
V2 alert_test hmac_alert_test 0.730s 20.167us 1 1 100.00
V2 intr_test hmac_intr_test 0.770s 13.003us 1 1 100.00
V2 tl_d_oob_addr_access hmac_tl_errors 2.600s 149.227us 1 1 100.00
V2 tl_d_illegal_access hmac_tl_errors 2.600s 149.227us 1 1 100.00
V2 tl_d_outstanding_access hmac_csr_hw_reset 0.870s 21.774us 1 1 100.00
hmac_csr_rw 0.700s 64.127us 1 1 100.00
hmac_csr_aliasing 2.520s 218.416us 1 1 100.00
hmac_same_csr_outstanding 1.040s 81.708us 1 1 100.00
V2 tl_d_partial_access hmac_csr_hw_reset 0.870s 21.774us 1 1 100.00
hmac_csr_rw 0.700s 64.127us 1 1 100.00
hmac_csr_aliasing 2.520s 218.416us 1 1 100.00
hmac_same_csr_outstanding 1.040s 81.708us 1 1 100.00
V2 TOTAL 17 17 100.00
V2S tl_intg_err hmac_sec_cm 0.980s 78.290us 1 1 100.00
hmac_tl_intg_err 1.640s 322.849us 1 1 100.00
V2S sec_cm_bus_integrity hmac_tl_intg_err 1.640s 322.849us 1 1 100.00
V2S TOTAL 2 2 100.00
V3 write_config_and_secret_key_during_msg_wr hmac_smoke 8.000s 861.583us 1 1 100.00
V3 stress_reset hmac_stress_reset 3.020s 694.987us 1 1 100.00
V3 stress_all_with_rand_reset hmac_stress_all_with_rand_reset 1.070m 18.988ms 1 1 100.00
V3 TOTAL 2 2 100.00
Unmapped tests hmac_directed 1.190s 26.810us 1 1 100.00
TOTAL 28 28 100.00