I2C Simulation Results

Thursday October 09 2025 19:22:42 UTC

GitHub Revision: 677ee3d

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	host_smoke	i2c_host_smoke	45.920s	2.883ms	1	1	100.00
V1	target_smoke	i2c_target_smoke	10.600s	2.860ms	1	1	100.00
V1	csr_hw_reset	i2c_csr_hw_reset	0.710s	22.106us	1	1	100.00
V1	csr_rw	i2c_csr_rw	0.840s	23.334us	1	1	100.00
V1	csr_bit_bash	i2c_csr_bit_bash	3.250s	430.454us	1	1	100.00
V1	csr_aliasing	i2c_csr_aliasing	1.430s	142.150us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	i2c_csr_mem_rw_with_rand_reset	1.300s	41.544us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	i2c_csr_rw	0.840s	23.334us	1	1	100.00
		i2c_csr_aliasing	1.430s	142.150us	1	1	100.00
V1		TOTAL			7	7	100.00
V2	host_error_intr	i2c_host_error_intr	0.890s	28.581us	0	1	0.00
V2	host_stress_all	i2c_host_stress_all	14.519m	35.446ms	0	1	0.00
V2	host_maxperf	i2c_host_perf	1.742m	13.095ms	1	1	100.00
V2	host_override	i2c_host_override	0.720s	55.436us	1	1	100.00
V2	host_fifo_watermark	i2c_host_fifo_watermark	4.116m	5.087ms	1	1	100.00
V2	host_fifo_overflow	i2c_host_fifo_overflow	1.575m	4.376ms	1	1	100.00
V2	host_fifo_reset	i2c_host_fifo_reset_fmt	1.380s	538.834us	1	1	100.00
		i2c_host_fifo_fmt_empty	3.380s	904.297us	1	1	100.00
		i2c_host_fifo_reset_rx	2.620s	143.160us	1	1	100.00
V2	host_fifo_full	i2c_host_fifo_full	49.040s	6.020ms	1	1	100.00
V2	host_timeout	i2c_host_stretch_timeout	6.480s	2.346ms	1	1	100.00
V2	i2c_host_mode_toggle	i2c_host_mode_toggle	0.860s	121.705us	0	1	0.00
V2	target_glitch	i2c_target_glitch	2.590s	526.856us	0	1	0.00
V2	target_stress_all	i2c_target_stress_all	1.897m	22.319ms	1	1	100.00
V2	target_maxperf	i2c_target_perf	3.090s	536.270us	1	1	100.00
V2	target_fifo_empty	i2c_target_stress_rd	11.030s	4.057ms	1	1	100.00
		i2c_target_intr_smoke	4.000s	826.647us	1	1	100.00
V2	target_fifo_reset	i2c_target_fifo_reset_acq	0.820s	671.120us	1	1	100.00
		i2c_target_fifo_reset_tx	1.120s	162.791us	1	1	100.00
V2	target_fifo_full	i2c_target_stress_wr	33.270s	34.357ms	1	1	100.00
		i2c_target_stress_rd	11.030s	4.057ms	1	1	100.00
		i2c_target_intr_stress_wr	3.090s	10.285ms	1	1	100.00
V2	target_timeout	i2c_target_timeout	3.880s	2.550ms	1	1	100.00
V2	target_clock_stretch	i2c_target_stretch	17.870s	3.562ms	1	1	100.00
V2	bad_address	i2c_target_bad_addr	3.240s	13.839ms	1	1	100.00
V2	target_mode_glitch	i2c_target_hrst	1.710s	200.048us	1	1	100.00
V2	target_fifo_watermark	i2c_target_fifo_watermarks_acq	1.670s	812.852us	1	1	100.00
		i2c_target_fifo_watermarks_tx	0.870s	295.546us	1	1	100.00
V2	host_mode_config_perf	i2c_host_perf	1.742m	13.095ms	1	1	100.00
		i2c_host_perf_precise	16.850s	6.029ms	1	1	100.00
V2	host_mode_clock_stretching	i2c_host_stretch_timeout	6.480s	2.346ms	1	1	100.00
V2	target_mode_tx_stretch_ctrl	i2c_target_tx_stretch_ctrl	1.560s	97.068us	1	1	100.00
V2	target_mode_nack_generation	i2c_target_nack_acqfull	2.040s	2.935ms	1	1	100.00
		i2c_target_nack_acqfull_addr	2.230s	538.287us	1	1	100.00
		i2c_target_nack_txstretch	1.110s	157.913us	1	1	100.00
V2	host_mode_halt_on_nak	i2c_host_may_nack	7.180s	2.825ms	1	1	100.00
V2	target_mode_smbus_maxlen	i2c_target_smbus_maxlen	1.640s	1.990ms	1	1	100.00
V2	alert_test	i2c_alert_test	0.730s	84.456us	1	1	100.00
V2	intr_test	i2c_intr_test	0.750s	50.469us	1	1	100.00
V2	tl_d_oob_addr_access	i2c_tl_errors	1.430s	303.085us	1	1	100.00
V2	tl_d_illegal_access	i2c_tl_errors	1.430s	303.085us	1	1	100.00
V2	tl_d_outstanding_access	i2c_csr_hw_reset	0.710s	22.106us	1	1	100.00
		i2c_csr_rw	0.840s	23.334us	1	1	100.00
		i2c_csr_aliasing	1.430s	142.150us	1	1	100.00
		i2c_same_csr_outstanding	1.000s	35.898us	1	1	100.00
V2	tl_d_partial_access	i2c_csr_hw_reset	0.710s	22.106us	1	1	100.00
		i2c_csr_rw	0.840s	23.334us	1	1	100.00
		i2c_csr_aliasing	1.430s	142.150us	1	1	100.00
		i2c_same_csr_outstanding	1.000s	35.898us	1	1	100.00
V2		TOTAL			34	38	89.47
V2S	tl_intg_err	i2c_tl_intg_err	2.020s	136.622us	1	1	100.00
		i2c_sec_cm	1.110s	65.969us	1	1	100.00
V2S	sec_cm_bus_integrity	i2c_tl_intg_err	2.020s	136.622us	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	host_stress_all_with_rand_reset	i2c_host_stress_all_with_rand_reset	4.000s	499.781us	0	1	0.00
V3	target_error_intr	i2c_target_unexp_stop	1.900s	888.843us	0	1	0.00
V3	target_stress_all_with_rand_reset	i2c_target_stress_all_with_rand_reset	6.260s	5.417ms	0	1	0.00
V3		TOTAL			0	3	0.00
		TOTAL			43	50	86.00

Failure Buckets

• UVM_ERROR sequencer [sequencer] Get_next_item called twice without item_done or get in between has 3 failures:

  • Test i2c_host_error_intr has 1 failures.

    • 0.i2c_host_error_intr.103918707050387321321324870774102032240857164415575162349317177329450972537932
      Line 91, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_host_error_intr/latest/run.log

        UVM_ERROR @  28581383 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] Get_next_item called twice without item_done or get in between
        UVM_INFO @  28581383 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test i2c_host_stress_all has 1 failures.

    • 0.i2c_host_stress_all.97589571159961198131138357071153107419920699988624840355599253381510871686209
      Line 162, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_host_stress_all/latest/run.log

        UVM_ERROR @ 35445995761 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] Get_next_item called twice without item_done or get in between
        UVM_INFO @ 35445995761 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test i2c_target_stress_all_with_rand_reset has 1 failures.

    • 0.i2c_target_stress_all_with_rand_reset.94933764859674740799699001543422576477402507278431574613203416479379526012966
      Line 89, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_target_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 5417340629 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] Get_next_item called twice without item_done or get in between
        UVM_INFO @ 5417340629 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR sequencer [sequencer] get_next_item/try_next_item called twice without item_done or get in between has 1 failures:

  • Test i2c_target_glitch has 1 failures.

    • 0.i2c_target_glitch.61477081666826197830495270881602725783334162992012590945231127465627789735523
      Line 81, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_target_glitch/latest/run.log

        UVM_ERROR @ 526856233 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] get_next_item/try_next_item called twice without item_done or get in between
        UVM_INFO @ 526856233 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (i2c_scoreboard.sv:682) [scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (* [*] vs * [*]) has 1 failures:

  • Test i2c_target_unexp_stop has 1 failures.

    • 0.i2c_target_unexp_stop.25453007659630681379359765327524674055206935612019727213347260148861102656396
      Line 75, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_target_unexp_stop/latest/run.log

        UVM_ERROR @ 888843015 ps: (i2c_scoreboard.sv:682) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 84 [0x54])
        UVM_INFO @ 888843015 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (cip_base_vseq.sv:1229) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:

  • Test i2c_host_stress_all_with_rand_reset has 1 failures.

    • 0.i2c_host_stress_all_with_rand_reset.5019721517674096947817103195406730803536025369482989067749571466900904383146
      Line 83, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_host_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 499780557 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 499780557 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout i2c_reg_block.status.hostidle (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=3) has 1 failures:

  • Test i2c_host_mode_toggle has 1 failures.

    • 0.i2c_host_mode_toggle.73340326867026427059963633611770639161091107881497750302171237260323289874196
      Line 76, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_host_mode_toggle/latest/run.log

        UVM_FATAL @ 121705224 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout i2c_reg_block.status.hostidle (addr=0x87a20914, Comparison=CompareOpEq, exp_data=0x1, call_count=3)
        UVM_INFO @ 121705224 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---