OTBN Simulation Results

Thursday October 09 2025 19:22:42 UTC

GitHub Revision: 677ee3d

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke otbn_smoke 8.000s 140.637us 0 1 0.00
V1 single_binary otbn_single 17.000s 83.688us 0 1 0.00
V1 csr_hw_reset otbn_csr_hw_reset 3.000s 27.297us 1 1 100.00
V1 csr_rw otbn_csr_rw 3.000s 19.553us 1 1 100.00
V1 csr_bit_bash otbn_csr_bit_bash 6.000s 374.465us 1 1 100.00
V1 csr_aliasing otbn_csr_aliasing 3.000s 17.569us 1 1 100.00
V1 csr_mem_rw_with_rand_reset otbn_csr_mem_rw_with_rand_reset 5.000s 91.957us 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr otbn_csr_rw 3.000s 19.553us 1 1 100.00
otbn_csr_aliasing 3.000s 17.569us 1 1 100.00
V1 mem_walk otbn_mem_walk 16.000s 669.607us 1 1 100.00
V1 mem_partial_access otbn_mem_partial_access 8.000s 70.251us 1 1 100.00
V1 TOTAL 7 9 77.78
V2 reset_recovery otbn_reset 27.000s 134.647us 0 1 0.00
V2 multi_error otbn_multi_err 33.000s 585.631us 0 1 0.00
V2 back_to_back otbn_multi 41.000s 222.179us 0 1 0.00
V2 stress_all otbn_stress_all 58.000s 233.081us 0 1 0.00
V2 lc_escalation otbn_escalate 5.000s 22.824us 1 1 100.00
V2 zero_state_err_urnd otbn_zero_state_err_urnd 5.000s 16.786us 0 1 0.00
V2 sw_errs_fatal_chk otbn_sw_errs_fatal_chk 7.000s 24.678us 0 1 0.00
V2 alert_test otbn_alert_test 4.000s 14.854us 1 1 100.00
V2 intr_test otbn_intr_test 3.000s 40.084us 1 1 100.00
V2 tl_d_oob_addr_access otbn_tl_errors 5.000s 82.066us 1 1 100.00
V2 tl_d_illegal_access otbn_tl_errors 5.000s 82.066us 1 1 100.00
V2 tl_d_outstanding_access otbn_csr_hw_reset 3.000s 27.297us 1 1 100.00
otbn_csr_rw 3.000s 19.553us 1 1 100.00
otbn_csr_aliasing 3.000s 17.569us 1 1 100.00
otbn_same_csr_outstanding 4.000s 56.093us 1 1 100.00
V2 tl_d_partial_access otbn_csr_hw_reset 3.000s 27.297us 1 1 100.00
otbn_csr_rw 3.000s 19.553us 1 1 100.00
otbn_csr_aliasing 3.000s 17.569us 1 1 100.00
otbn_same_csr_outstanding 4.000s 56.093us 1 1 100.00
V2 TOTAL 5 11 45.45
V2S mem_integrity otbn_imem_err 7.000s 17.947us 0 1 0.00
otbn_dmem_err 5.000s 15.707us 0 1 0.00
V2S internal_integrity otbn_alu_bignum_mod_err 8.000s 60.684us 0 1 0.00
otbn_controller_ispr_rdata_err 8.000s 117.807us 0 1 0.00
otbn_mac_bignum_acc_err 7.000s 31.475us 0 1 0.00
otbn_urnd_err 7.000s 34.797us 0 1 0.00
V2S illegal_bus_access otbn_illegal_mem_acc 7.000s 26.742us 1 1 100.00
V2S otbn_mem_gnt_acc_err otbn_mem_gnt_acc_err 5.000s 52.245us 1 1 100.00
V2S otbn_non_sec_partial_wipe otbn_partial_wipe 5.000s 298.338us 1 1 100.00
V2S tl_intg_err otbn_sec_cm 4.000s 9.683us 0 1 0.00
otbn_tl_intg_err 9.000s 1.044ms 1 1 100.00
V2S passthru_mem_tl_intg_err otbn_passthru_mem_tl_intg_err 27.000s 226.792us 1 1 100.00
V2S prim_fsm_check otbn_sec_cm 4.000s 9.683us 0 1 0.00
V2S prim_count_check otbn_sec_cm 4.000s 9.683us 0 1 0.00
V2S sec_cm_mem_scramble otbn_smoke 8.000s 140.637us 0 1 0.00
V2S sec_cm_data_mem_integrity otbn_dmem_err 5.000s 15.707us 0 1 0.00
V2S sec_cm_instruction_mem_integrity otbn_imem_err 7.000s 17.947us 0 1 0.00
V2S sec_cm_bus_integrity otbn_tl_intg_err 9.000s 1.044ms 1 1 100.00
V2S sec_cm_controller_fsm_global_esc otbn_escalate 5.000s 22.824us 1 1 100.00
V2S sec_cm_controller_fsm_local_esc otbn_imem_err 7.000s 17.947us 0 1 0.00
otbn_dmem_err 5.000s 15.707us 0 1 0.00
otbn_zero_state_err_urnd 5.000s 16.786us 0 1 0.00
otbn_illegal_mem_acc 7.000s 26.742us 1 1 100.00
otbn_sec_cm 4.000s 9.683us 0 1 0.00
V2S sec_cm_controller_fsm_sparse otbn_sec_cm 4.000s 9.683us 0 1 0.00
V2S sec_cm_scramble_key_sideload otbn_single 17.000s 83.688us 0 1 0.00
V2S sec_cm_scramble_ctrl_fsm_local_esc otbn_imem_err 7.000s 17.947us 0 1 0.00
otbn_dmem_err 5.000s 15.707us 0 1 0.00
otbn_zero_state_err_urnd 5.000s 16.786us 0 1 0.00
otbn_illegal_mem_acc 7.000s 26.742us 1 1 100.00
otbn_sec_cm 4.000s 9.683us 0 1 0.00
V2S sec_cm_scramble_ctrl_fsm_sparse otbn_sec_cm 4.000s 9.683us 0 1 0.00
V2S sec_cm_start_stop_ctrl_fsm_global_esc otbn_escalate 5.000s 22.824us 1 1 100.00
V2S sec_cm_start_stop_ctrl_fsm_local_esc otbn_imem_err 7.000s 17.947us 0 1 0.00
otbn_dmem_err 5.000s 15.707us 0 1 0.00
otbn_zero_state_err_urnd 5.000s 16.786us 0 1 0.00
otbn_illegal_mem_acc 7.000s 26.742us 1 1 100.00
otbn_sec_cm 4.000s 9.683us 0 1 0.00
V2S sec_cm_start_stop_ctrl_fsm_sparse otbn_sec_cm 4.000s 9.683us 0 1 0.00
V2S sec_cm_data_reg_sw_sca otbn_single 17.000s 83.688us 0 1 0.00
V2S sec_cm_ctrl_redun otbn_ctrl_redun 7.000s 96.578us 0 1 0.00
V2S sec_cm_pc_ctrl_flow_redun otbn_pc_ctrl_flow_redun 6.000s 322.694us 1 1 100.00
V2S sec_cm_rnd_bus_consistency otbn_rnd_sec_cm 25.000s 613.818us 0 1 0.00
V2S sec_cm_rnd_rng_digest otbn_rnd_sec_cm 25.000s 613.818us 0 1 0.00
V2S sec_cm_rf_base_data_reg_sw_integrity otbn_rf_base_intg_err 8.000s 26.322us 0 1 0.00
V2S sec_cm_rf_base_data_reg_sw_glitch_detect otbn_sec_cm 4.000s 9.683us 0 1 0.00
V2S sec_cm_stack_wr_ptr_ctr_redun otbn_sec_cm 4.000s 9.683us 0 1 0.00
V2S sec_cm_rf_bignum_data_reg_sw_integrity otbn_rf_bignum_intg_err 6.000s 214.222us 0 1 0.00
V2S sec_cm_rf_bignum_data_reg_sw_glitch_detect otbn_sec_cm 4.000s 9.683us 0 1 0.00
V2S sec_cm_loop_stack_ctr_redun otbn_sec_cm 4.000s 9.683us 0 1 0.00
V2S sec_cm_loop_stack_addr_integrity otbn_stack_addr_integ_chk 5.000s 91.673us 0 1 0.00
V2S sec_cm_call_stack_addr_integrity otbn_stack_addr_integ_chk 5.000s 91.673us 0 1 0.00
V2S sec_cm_start_stop_ctrl_state_consistency otbn_sec_wipe_err 4.000s 21.103us 1 1 100.00
V2S sec_cm_data_mem_sec_wipe otbn_single 17.000s 83.688us 0 1 0.00
V2S sec_cm_instruction_mem_sec_wipe otbn_single 17.000s 83.688us 0 1 0.00
V2S sec_cm_data_reg_sw_sec_wipe otbn_single 17.000s 83.688us 0 1 0.00
V2S sec_cm_write_mem_integrity otbn_multi 41.000s 222.179us 0 1 0.00
V2S sec_cm_ctrl_flow_count otbn_single 17.000s 83.688us 0 1 0.00
V2S sec_cm_ctrl_flow_sca otbn_single 17.000s 83.688us 0 1 0.00
V2S sec_cm_data_mem_sw_noaccess otbn_sw_no_acc 5.000s 101.324us 0 1 0.00
V2S sec_cm_key_sideload otbn_single 17.000s 83.688us 0 1 0.00
V2S sec_cm_tlul_fifo_ctr_redun otbn_sec_cm 4.000s 9.683us 0 1 0.00
V2S TOTAL 7 20 35.00
V3 stress_all_with_rand_reset otbn_stress_all_with_rand_reset 4.567m 1.114ms 0 1 0.00
V3 TOTAL 0 1 0.00
TOTAL 19 41 46.34

Failure Buckets