PATTGEN Simulation Results

Thursday October 09 2025 19:22:42 UTC

GitHub Revision: 677ee3d

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	pattgen_smoke	2.000s	106.214us	1	1	100.00
V1	csr_hw_reset	pattgen_csr_hw_reset	1.000s	23.372us	1	1	100.00
V1	csr_rw	pattgen_csr_rw	2.000s	13.891us	1	1	100.00
V1	csr_bit_bash	pattgen_csr_bit_bash	2.000s	142.319us	1	1	100.00
V1	csr_aliasing	pattgen_csr_aliasing	2.000s	27.838us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	pattgen_csr_mem_rw_with_rand_reset	2.000s	123.926us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	pattgen_csr_rw	2.000s	13.891us	1	1	100.00
		pattgen_csr_aliasing	2.000s	27.838us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	perf	pattgen_perf			0	1	0.00
V2	cnt_rollover	cnt_rollover	59.000s	9.082ms	1	1	100.00
V2	error	pattgen_error	2.000s	22.031us	1	1	100.00
V2	stress_all	pattgen_stress_all	2.150m	44.654ms	0	1	0.00
V2	alert_test	pattgen_alert_test	1.000s	10.053us	1	1	100.00
V2	intr_test	pattgen_intr_test	1.000s	102.758us	1	1	100.00
V2	tl_d_oob_addr_access	pattgen_tl_errors	2.000s	37.043us	1	1	100.00
V2	tl_d_illegal_access	pattgen_tl_errors	2.000s	37.043us	1	1	100.00
V2	tl_d_outstanding_access	pattgen_csr_hw_reset	1.000s	23.372us	1	1	100.00
		pattgen_csr_rw	2.000s	13.891us	1	1	100.00
		pattgen_csr_aliasing	2.000s	27.838us	1	1	100.00
		pattgen_same_csr_outstanding	2.000s	15.635us	1	1	100.00
V2	tl_d_partial_access	pattgen_csr_hw_reset	1.000s	23.372us	1	1	100.00
		pattgen_csr_rw	2.000s	13.891us	1	1	100.00
		pattgen_csr_aliasing	2.000s	27.838us	1	1	100.00
		pattgen_same_csr_outstanding	2.000s	15.635us	1	1	100.00
V2		TOTAL			6	8	75.00
V2S	tl_intg_err	pattgen_tl_intg_err	1.000s	41.316us	1	1	100.00
		pattgen_sec_cm	1.000s	197.774us	1	1	100.00
V2S	sec_cm_bus_integrity	pattgen_tl_intg_err	1.000s	41.316us	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	stress_all_with_rand_reset	pattgen_stress_all_with_rand_reset	33.000s	3.977ms	0	1	0.00
V3		TOTAL			0	1	0.00
	Unmapped tests	pattgen_inactive_level	2.000s	381.269us	1	1	100.00
		TOTAL			15	18	83.33

Failure Buckets

• Job timed out after * minutes has 1 failures:

  • Test pattgen_perf has 1 failures.

    • 0.pattgen_perf.3827111730360284984178523274220363611703387207126573586489231928099847448296
      Log /nightly/current_run/scratch/master/pattgen-sim-xcelium/0.pattgen_perf/latest/run.log

        Job timed out after 60 minutes
      

• UVM_ERROR (cip_base_vseq.sv:1230) [pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:

  • Test pattgen_stress_all_with_rand_reset has 1 failures.

    • 0.pattgen_stress_all_with_rand_reset.92939456163726966919647252460227290156858534677421472232923480750026842943749
      Line 113, in log /nightly/current_run/scratch/master/pattgen-sim-xcelium/0.pattgen_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 590883141 ps: (cip_base_vseq.sv:1230) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_ERROR @ 590891545 ps: (cip_base_vseq.sv:1143) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
        UVM_INFO @ 590891545 ps: (cip_base_vseq.sv:1146) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
        Issuing reset for run 1/10
        UVM_INFO @ 590991545 ps: (cip_base_vseq.sv:1167) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
      

• UVM_ERROR (pattgen_scoreboard.sv:76) [scoreboard] exp_item_q[i] item uncompared: has 1 failures:

  • Test pattgen_stress_all has 1 failures.

    • 0.pattgen_stress_all.67790697121017193623621535581541427944180107059058896666056689103059991718339
      Line 122, in log /nightly/current_run/scratch/master/pattgen-sim-xcelium/0.pattgen_stress_all/latest/run.log

        UVM_ERROR @ 44654076936 ps: (pattgen_scoreboard.sv:76) [uvm_test_top.env.scoreboard] exp_item_q[i] item uncompared:
        ----------------------------------------
        Name         Type          Size   Value
        ----------------------------------------
        exp_item     pattgen_item  -      @10199