RV_TIMER Simulation Results

Thursday October 09 2025 19:22:42 UTC

GitHub Revision: 677ee3d

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	random	rv_timer_random	0.830s	237.527us	1	1	100.00
V1	csr_hw_reset	rv_timer_csr_hw_reset	0.620s	24.471us	1	1	100.00
V1	csr_rw	rv_timer_csr_rw	0.720s	126.995us	1	1	100.00
V1	csr_bit_bash	rv_timer_csr_bit_bash	1.470s	604.417us	1	1	100.00
V1	csr_aliasing	rv_timer_csr_aliasing	0.690s	41.438us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	rv_timer_csr_mem_rw_with_rand_reset	0.690s	17.676us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rv_timer_csr_rw	0.720s	126.995us	1	1	100.00
		rv_timer_csr_aliasing	0.690s	41.438us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	random_reset	rv_timer_random_reset	0.740s	92.869us	0	1	0.00
V2	disabled	rv_timer_disabled	1.420s	1.533ms	1	1	100.00
V2	cfg_update_on_fly	rv_timer_cfg_update_on_fly	1.560m	81.533ms	1	1	100.00
V2	no_interrupt_test	rv_timer_cfg_update_on_fly	1.560m	81.533ms	1	1	100.00
V2	stress	rv_timer_stress_all	2.640s	1.668ms	1	1	100.00
V2	alert_test	rv_timer_alert_test	0.760s	41.356us	1	1	100.00
V2	intr_test	rv_timer_intr_test	0.580s	74.118us	1	1	100.00
V2	tl_d_oob_addr_access	rv_timer_tl_errors	2.190s	1.144ms	1	1	100.00
V2	tl_d_illegal_access	rv_timer_tl_errors	2.190s	1.144ms	1	1	100.00
V2	tl_d_outstanding_access	rv_timer_csr_hw_reset	0.620s	24.471us	1	1	100.00
		rv_timer_csr_rw	0.720s	126.995us	1	1	100.00
		rv_timer_csr_aliasing	0.690s	41.438us	1	1	100.00
		rv_timer_same_csr_outstanding	0.870s	20.242us	1	1	100.00
V2	tl_d_partial_access	rv_timer_csr_hw_reset	0.620s	24.471us	1	1	100.00
		rv_timer_csr_rw	0.720s	126.995us	1	1	100.00
		rv_timer_csr_aliasing	0.690s	41.438us	1	1	100.00
		rv_timer_same_csr_outstanding	0.870s	20.242us	1	1	100.00
V2		TOTAL			7	8	87.50
V2S	tl_intg_err	rv_timer_sec_cm	0.810s	38.846us	1	1	100.00
		rv_timer_tl_intg_err	1.440s	386.154us	1	1	100.00
V2S	sec_cm_bus_integrity	rv_timer_tl_intg_err	1.440s	386.154us	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	min_value	rv_timer_min	0.930s	517.318us	0	1	0.00
V3	max_value	rv_timer_max	0.590s	13.521us	1	1	100.00
V3	stress_all_with_rand_reset	rv_timer_stress_all_with_rand_reset	10.910s	3.369ms	1	1	100.00
V3		TOTAL			2	3	66.67
		TOTAL			17	19	89.47

Failure Buckets

• UVM_FATAL (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state* (addr=*) == * has 2 failures:

  • Test rv_timer_min has 1 failures.

    • 0.rv_timer_min.81024641331956210609032226359814316967534632284607406099582666239338602685455
      Line 72, in log /nightly/current_run/scratch/master/rv_timer-sim-vcs/0.rv_timer_min/latest/run.log

        UVM_FATAL @ 517317894 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0xecec9904) == 0x1
        UVM_INFO @ 517317894 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test rv_timer_random_reset has 1 failures.

    • 0.rv_timer_random_reset.59508044121856223782014603962839079999713367305095873665804409657031708256145
      Line 72, in log /nightly/current_run/scratch/master/rv_timer-sim-vcs/0.rv_timer_random_reset/latest/run.log

        UVM_FATAL @  92868698 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0x608a8104) == 0x1
        UVM_INFO @  92868698 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---