SPI_DEVICE/1R1W Simulation Results

Thursday October 09 2025 19:22:42 UTC

GitHub Revision: 677ee3d

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_device_flash_and_tpm	2.544m	101.080ms	1	1	100.00
V1	csr_hw_reset	spi_device_csr_hw_reset	1.320s	21.374us	1	1	100.00
V1	csr_rw	spi_device_csr_rw	1.250s	74.075us	1	1	100.00
V1	csr_bit_bash	spi_device_csr_bit_bash	17.200s	4.673ms	1	1	100.00
V1	csr_aliasing	spi_device_csr_aliasing	11.020s	2.515ms	1	1	100.00
V1	csr_mem_rw_with_rand_reset	spi_device_csr_mem_rw_with_rand_reset	2.060s	159.645us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_device_csr_rw	1.250s	74.075us	1	1	100.00
		spi_device_csr_aliasing	11.020s	2.515ms	1	1	100.00
V1	mem_walk	spi_device_mem_walk	0.890s	12.357us	1	1	100.00
V1	mem_partial_access	spi_device_mem_partial_access	2.060s	83.648us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	csb_read	spi_device_csb_read	0.900s	46.873us	1	1	100.00
V2	mem_parity	spi_device_mem_parity	0.830s	1.869us	0	1	0.00
V2	mem_cfg	spi_device_ram_cfg	0.740s	16.592us	0	1	0.00
V2	tpm_read	spi_device_tpm_rw	1.430s	176.384us	1	1	100.00
V2	tpm_write	spi_device_tpm_rw	1.430s	176.384us	1	1	100.00
V2	tpm_hw_reg	spi_device_tpm_read_hw_reg	2.230s	1.270ms	1	1	100.00
		spi_device_tpm_sts_read	1.060s	19.109us	1	1	100.00
V2	tpm_fully_random_case	spi_device_tpm_all	6.960s	3.916ms	1	1	100.00
V2	pass_cmd_filtering	spi_device_pass_cmd_filtering	3.550s	2.996ms	1	1	100.00
		spi_device_flash_all	43.750s	58.252ms	1	1	100.00
V2	pass_addr_translation	spi_device_pass_addr_payload_swap	5.520s	3.102ms	1	1	100.00
		spi_device_flash_all	43.750s	58.252ms	1	1	100.00
V2	pass_payload_translation	spi_device_pass_addr_payload_swap	5.520s	3.102ms	1	1	100.00
		spi_device_flash_all	43.750s	58.252ms	1	1	100.00
V2	cmd_info_slots	spi_device_flash_all	43.750s	58.252ms	1	1	100.00
V2	cmd_read_status	spi_device_intercept	7.860s	3.835ms	1	1	100.00
		spi_device_flash_all	43.750s	58.252ms	1	1	100.00
V2	cmd_read_jedec	spi_device_intercept	7.860s	3.835ms	1	1	100.00
		spi_device_flash_all	43.750s	58.252ms	1	1	100.00
V2	cmd_read_sfdp	spi_device_intercept	7.860s	3.835ms	1	1	100.00
		spi_device_flash_all	43.750s	58.252ms	1	1	100.00
V2	cmd_fast_read	spi_device_intercept	7.860s	3.835ms	1	1	100.00
		spi_device_flash_all	43.750s	58.252ms	1	1	100.00
V2	cmd_read_pipeline	spi_device_intercept	7.860s	3.835ms	1	1	100.00
		spi_device_flash_all	43.750s	58.252ms	1	1	100.00
V2	flash_cmd_upload	spi_device_upload	2.190s	378.695us	1	1	100.00
V2	mailbox_command	spi_device_mailbox	12.100s	5.871ms	1	1	100.00
V2	mailbox_cross_outside_command	spi_device_mailbox	12.100s	5.871ms	1	1	100.00
V2	mailbox_cross_inside_command	spi_device_mailbox	12.100s	5.871ms	1	1	100.00
V2	cmd_read_buffer	spi_device_flash_mode	10.970s	3.197ms	1	1	100.00
		spi_device_read_buffer_direct	7.790s	2.925ms	1	1	100.00
V2	cmd_dummy_cycle	spi_device_mailbox	12.100s	5.871ms	1	1	100.00
		spi_device_flash_all	43.750s	58.252ms	1	1	100.00
V2	quad_spi	spi_device_flash_all	43.750s	58.252ms	1	1	100.00
V2	dual_spi	spi_device_flash_all	43.750s	58.252ms	1	1	100.00
V2	4b_3b_feature	spi_device_cfg_cmd	3.740s	521.097us	1	1	100.00
V2	write_enable_disable	spi_device_cfg_cmd	3.740s	521.097us	1	1	100.00
V2	TPM_with_flash_or_passthrough_mode	spi_device_flash_and_tpm	2.544m	101.080ms	1	1	100.00
V2	tpm_and_flash_trans_with_min_inactive_time	spi_device_flash_and_tpm_min_idle	3.422m	133.715ms	1	1	100.00
V2	stress_all	spi_device_stress_all	30.980s	8.968ms	1	1	100.00
V2	alert_test	spi_device_alert_test	0.700s	63.321us	1	1	100.00
V2	intr_test	spi_device_intr_test	0.920s	41.596us	1	1	100.00
V2	tl_d_oob_addr_access	spi_device_tl_errors	2.230s	155.418us	1	1	100.00
V2	tl_d_illegal_access	spi_device_tl_errors	2.230s	155.418us	1	1	100.00
V2	tl_d_outstanding_access	spi_device_csr_hw_reset	1.320s	21.374us	1	1	100.00
		spi_device_csr_rw	1.250s	74.075us	1	1	100.00
		spi_device_csr_aliasing	11.020s	2.515ms	1	1	100.00
		spi_device_same_csr_outstanding	2.410s	160.155us	1	1	100.00
V2	tl_d_partial_access	spi_device_csr_hw_reset	1.320s	21.374us	1	1	100.00
		spi_device_csr_rw	1.250s	74.075us	1	1	100.00
		spi_device_csr_aliasing	11.020s	2.515ms	1	1	100.00
		spi_device_same_csr_outstanding	2.410s	160.155us	1	1	100.00
V2		TOTAL			20	22	90.91
V2S	tl_intg_err	spi_device_sec_cm	1.550s	179.381us	1	1	100.00
		spi_device_tl_intg_err	10.120s	193.934us	1	1	100.00
V2S	sec_cm_bus_integrity	spi_device_tl_intg_err	10.120s	193.934us	1	1	100.00
V2S		TOTAL			2	2	100.00
	Unmapped tests	spi_device_flash_mode_ignore_cmds	1.141m	61.622ms	1	1	100.00
		TOTAL			31	33	93.94

Failure Buckets

• UVM_ERROR (uvm_hdl_vcs.c:1035) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[*]) has 1 failures:

  • Test spi_device_mem_parity has 1 failures.

    • 0.spi_device_mem_parity.70097181671828476759931505072788551380979961612924778513181852438107286989604
      Line 73, in log /nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/0.spi_device_mem_parity/latest/run.log

        UVM_ERROR @   1494480 ps: (uvm_hdl_vcs.c:1035) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[24])
         Either the name is incorrect, or you may not have PLI/ACC visibility to that name
        UVM_ERROR @   1494480 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
        UVM_ERROR @   1494480 ps: (uvm_hdl_vcs.c:1185) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[920])
         Either the name is incorrect, or you may not have PLI/ACC visibility to that name
      

• UVM_ERROR (spi_device_ram_cfg_vseq.sv:27) [spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (* [*] vs * [*]) has 1 failures:

  • Test spi_device_ram_cfg has 1 failures.

    • 0.spi_device_ram_cfg.4403609102969579679284583211398281033857832370890349633086699235242497816619
      Line 73, in log /nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/0.spi_device_ram_cfg/latest/run.log

        UVM_ERROR @  14195956 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x8c3933 [100011000011100100110011] vs 0x0 [0])
        UVM_ERROR @  14259956 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xa40176 [101001000000000101110110] vs 0x0 [0])
        UVM_ERROR @  14317956 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xd8c5e4 [110110001100010111100100] vs 0x0 [0])
        UVM_ERROR @  14400956 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x27c338 [1001111100001100111000] vs 0x0 [0])
        UVM_ERROR @  14462956 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x7a87e4 [11110101000011111100100] vs 0x0 [0])