SPI_HOST Simulation Results

Thursday October 09 2025 19:22:42 UTC

GitHub Revision: 677ee3d

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_host_smoke	35.000s	3.540ms	1	1	100.00
V1	csr_hw_reset	spi_host_csr_hw_reset	1.000s	57.130us	1	1	100.00
V1	csr_rw	spi_host_csr_rw	1.000s	24.337us	1	1	100.00
V1	csr_bit_bash	spi_host_csr_bit_bash	3.000s	1.297ms	1	1	100.00
V1	csr_aliasing	spi_host_csr_aliasing	1.000s	107.663us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	spi_host_csr_mem_rw_with_rand_reset	2.000s	21.980us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_host_csr_rw	1.000s	24.337us	1	1	100.00
		spi_host_csr_aliasing	1.000s	107.663us	1	1	100.00
V1	mem_walk	spi_host_mem_walk	1.000s	58.371us	1	1	100.00
V1	mem_partial_access	spi_host_mem_partial_access	1.000s	15.889us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	performance	spi_host_performance	2.000s	28.254us	1	1	100.00
V2	error_event_intr	spi_host_overflow_underflow	2.000s	221.603us	1	1	100.00
		spi_host_error_cmd	2.000s	64.144us	1	1	100.00
		spi_host_event	4.000s	227.219us	1	1	100.00
V2	clock_rate	spi_host_speed	2.650m	200.000ms	0	1	0.00
V2	speed	spi_host_speed	2.650m	200.000ms	0	1	0.00
V2	chip_select_timing	spi_host_speed	2.650m	200.000ms	0	1	0.00
V2	sw_reset	spi_host_sw_reset	4.000s	126.131us	1	1	100.00
V2	passthrough_mode	spi_host_passthrough_mode	2.000s	48.110us	1	1	100.00
V2	cpol_cpha	spi_host_speed	2.650m	200.000ms	0	1	0.00
V2	full_cycle	spi_host_speed	2.650m	200.000ms	0	1	0.00
V2	duplex	spi_host_smoke	35.000s	3.540ms	1	1	100.00
V2	tx_rx_only	spi_host_smoke	35.000s	3.540ms	1	1	100.00
V2	stress_all	spi_host_stress_all	2.000s	132.124us	1	1	100.00
V2	spien	spi_host_spien	3.000s	1.317ms	1	1	100.00
V2	stall	spi_host_status_stall	1.117m	2.168ms	1	1	100.00
V2	Idlecsbactive	spi_host_idlecsbactive	2.000s	114.729us	1	1	100.00
V2	data_fifo_status	spi_host_overflow_underflow	2.000s	221.603us	1	1	100.00
V2	alert_test	spi_host_alert_test	2.000s	87.872us	1	1	100.00
V2	intr_test	spi_host_intr_test	1.000s	18.414us	1	1	100.00
V2	tl_d_oob_addr_access	spi_host_tl_errors	2.000s	157.982us	1	1	100.00
V2	tl_d_illegal_access	spi_host_tl_errors	2.000s	157.982us	1	1	100.00
V2	tl_d_outstanding_access	spi_host_csr_hw_reset	1.000s	57.130us	1	1	100.00
		spi_host_csr_rw	1.000s	24.337us	1	1	100.00
		spi_host_csr_aliasing	1.000s	107.663us	1	1	100.00
		spi_host_same_csr_outstanding	1.000s	22.768us	1	1	100.00
V2	tl_d_partial_access	spi_host_csr_hw_reset	1.000s	57.130us	1	1	100.00
		spi_host_csr_rw	1.000s	24.337us	1	1	100.00
		spi_host_csr_aliasing	1.000s	107.663us	1	1	100.00
		spi_host_same_csr_outstanding	1.000s	22.768us	1	1	100.00
V2		TOTAL			14	15	93.33
V2S	tl_intg_err	spi_host_tl_intg_err	2.000s	116.911us	1	1	100.00
		spi_host_sec_cm	1.000s	43.061us	1	1	100.00
V2S	sec_cm_bus_integrity	spi_host_tl_intg_err	2.000s	116.911us	1	1	100.00
V2S		TOTAL			2	2	100.00
	Unmapped tests	spi_host_upper_range_clkdiv	8.067m	30.906ms	1	1	100.00
		TOTAL			25	26	96.15

Failure Buckets

• UVM_FATAL (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
  • Test spi_host_speed has 1 failures.

    • 0.spi_host_speed.28630073569060200254384716283868178734676286763166081115575718107037931179525
      Line 161, in log /nightly/current_run/scratch/master/spi_host-sim-xcelium/0.spi_host_speed/latest/run.log

        UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
        UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---