SRAM_CTRL/MAIN Simulation Results

Thursday October 09 2025 19:22:42 UTC

GitHub Revision: 677ee3d

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	11.640s	2.099ms	1	1	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	0.820s	43.201us	1	1	100.00
V1	csr_rw	sram_ctrl_csr_rw	0.860s	10.900us	1	1	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	1.640s	79.837us	1	1	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	0.810s	46.013us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	3.770s	1.428ms	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	0.860s	10.900us	1	1	100.00
		sram_ctrl_csr_aliasing	0.810s	46.013us	1	1	100.00
V1	mem_walk	sram_ctrl_mem_walk	2.398m	37.024ms	1	1	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	1.780m	4.997ms	1	1	100.00
V1		TOTAL			8	8	100.00
V2	multiple_keys	sram_ctrl_multiple_keys	9.106m	55.790ms	1	1	100.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	2.468m	13.495ms	1	1	100.00
V2	bijection	sram_ctrl_bijection	15.488m	18.697ms	1	1	100.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	7.329m	14.412ms	1	1	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	21.990s	8.985ms	1	1	100.00
V2	executable	sram_ctrl_executable	13.566m	23.957ms	1	1	100.00
V2	partial_access	sram_ctrl_partial_access	28.070s	14.819ms	1	1	100.00
		sram_ctrl_partial_access_b2b	4.985m	6.499ms	1	1	100.00
V2	max_throughput	sram_ctrl_max_throughput	1.044m	3.060ms	1	1	100.00
		sram_ctrl_throughput_w_partial_write	19.260s	2.903ms	1	1	100.00
		sram_ctrl_throughput_w_readback	26.810s	15.832ms	1	1	100.00
V2	regwen	sram_ctrl_regwen	8.544m	131.277ms	1	1	100.00
V2	ram_cfg	sram_ctrl_ram_cfg	5.100s	2.584ms	1	1	100.00
V2	stress_all	sram_ctrl_stress_all	54.846m	118.775ms	1	1	100.00
V2	alert_test	sram_ctrl_alert_test	0.950s	17.069us	1	1	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	3.400s	88.231us	1	1	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	3.400s	88.231us	1	1	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	0.820s	43.201us	1	1	100.00
		sram_ctrl_csr_rw	0.860s	10.900us	1	1	100.00
		sram_ctrl_csr_aliasing	0.810s	46.013us	1	1	100.00
		sram_ctrl_same_csr_outstanding	0.740s	61.262us	1	1	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	0.820s	43.201us	1	1	100.00
		sram_ctrl_csr_rw	0.860s	10.900us	1	1	100.00
		sram_ctrl_csr_aliasing	0.810s	46.013us	1	1	100.00
		sram_ctrl_same_csr_outstanding	0.740s	61.262us	1	1	100.00
V2		TOTAL			17	17	100.00
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	43.690s	46.974ms	1	1	100.00
V2S	tl_intg_err	sram_ctrl_sec_cm	0.850s	7.499us	0	1	0.00
		sram_ctrl_tl_intg_err	2.030s	187.713us	1	1	100.00
V2S	prim_count_check	sram_ctrl_sec_cm	0.850s	7.499us	0	1	0.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	2.030s	187.713us	1	1	100.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	8.544m	131.277ms	1	1	100.00
V2S	sec_cm_readback_config_regwen	sram_ctrl_regwen	8.544m	131.277ms	1	1	100.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	0.860s	10.900us	1	1	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	13.566m	23.957ms	1	1	100.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	13.566m	23.957ms	1	1	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	13.566m	23.957ms	1	1	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	21.990s	8.985ms	1	1	100.00
V2S	sec_cm_prim_ram_ctrl_mubi	sram_ctrl_mubi_enc_err	5.670s	3.895ms	1	1	100.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	43.690s	46.974ms	1	1	100.00
V2S	sec_cm_mem_readback	sram_ctrl_readback_err	5.030s	2.636ms	1	1	100.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	11.640s	2.099ms	1	1	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	11.640s	2.099ms	1	1	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	13.566m	23.957ms	1	1	100.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	0.850s	7.499us	0	1	0.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	21.990s	8.985ms	1	1	100.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	0.850s	7.499us	0	1	0.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	0.850s	7.499us	0	1	0.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	11.640s	2.099ms	1	1	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	0.850s	7.499us	0	1	0.00
V2S		TOTAL			4	5	80.00
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	36.340s	10.956ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			30	31	96.77

Failure Buckets

• Offending '(!$isunknown(rdata_o))' has 1 failures:
  • Test sram_ctrl_sec_cm has 1 failures.

    • 0.sram_ctrl_sec_cm.80605263711252229082702757168776538426656456780598846445841254675446071386588
      Line 96, in log /nightly/current_run/scratch/master/sram_ctrl_main-sim-vcs/0.sram_ctrl_sec_cm/latest/run.log

            Offending '(!$isunknown(rdata_o))'
        UVM_ERROR @   7498878 ps: (prim_fifo_sync.sv:224) [ASSERT FAILED] DataKnown_A
        UVM_INFO @   7498878 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---