SRAM_CTRL/RET Simulation Results

Thursday October 09 2025 19:22:42 UTC

GitHub Revision: 677ee3d

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	10.790s	2.656ms	1	1	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	0.660s	17.212us	1	1	100.00
V1	csr_rw	sram_ctrl_csr_rw	0.670s	14.951us	1	1	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	1.510s	275.690us	1	1	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	0.650s	15.760us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	0.850s	91.121us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	0.670s	14.951us	1	1	100.00
		sram_ctrl_csr_aliasing	0.650s	15.760us	1	1	100.00
V1	mem_walk	sram_ctrl_mem_walk	3.880s	98.024us	1	1	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	2.360s	626.343us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	multiple_keys	sram_ctrl_multiple_keys	6.143m	21.260ms	1	1	100.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	2.240m	2.007ms	1	1	100.00
V2	bijection	sram_ctrl_bijection	55.320s	7.070ms	1	1	100.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	1.447m	1.146ms	1	1	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	3.580s	327.784us	1	1	100.00
V2	executable	sram_ctrl_executable	5.203m	1.599ms	1	1	100.00
V2	partial_access	sram_ctrl_partial_access	33.330s	10.430ms	1	1	100.00
		sram_ctrl_partial_access_b2b	3.209m	35.767ms	1	1	100.00
V2	max_throughput	sram_ctrl_max_throughput	3.110s	81.476us	1	1	100.00
		sram_ctrl_throughput_w_partial_write	24.670s	252.910us	1	1	100.00
		sram_ctrl_throughput_w_readback	1.520s	89.873us	1	1	100.00
V2	regwen	sram_ctrl_regwen	2.746m	1.125ms	1	1	100.00
V2	ram_cfg	sram_ctrl_ram_cfg	0.660s	99.037us	1	1	100.00
V2	stress_all	sram_ctrl_stress_all	8.043m	13.427ms	1	1	100.00
V2	alert_test	sram_ctrl_alert_test	0.630s	18.058us	1	1	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	1.700s	86.925us	1	1	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	1.700s	86.925us	1	1	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	0.660s	17.212us	1	1	100.00
		sram_ctrl_csr_rw	0.670s	14.951us	1	1	100.00
		sram_ctrl_csr_aliasing	0.650s	15.760us	1	1	100.00
		sram_ctrl_same_csr_outstanding	0.660s	19.412us	1	1	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	0.660s	17.212us	1	1	100.00
		sram_ctrl_csr_rw	0.670s	14.951us	1	1	100.00
		sram_ctrl_csr_aliasing	0.650s	15.760us	1	1	100.00
		sram_ctrl_same_csr_outstanding	0.660s	19.412us	1	1	100.00
V2		TOTAL			17	17	100.00
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	2.190s	372.174us	1	1	100.00
V2S	tl_intg_err	sram_ctrl_sec_cm	0.630s	14.312us	0	1	0.00
		sram_ctrl_tl_intg_err	1.770s	292.447us	1	1	100.00
V2S	prim_count_check	sram_ctrl_sec_cm	0.630s	14.312us	0	1	0.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	1.770s	292.447us	1	1	100.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	2.746m	1.125ms	1	1	100.00
V2S	sec_cm_readback_config_regwen	sram_ctrl_regwen	2.746m	1.125ms	1	1	100.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	0.670s	14.951us	1	1	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	5.203m	1.599ms	1	1	100.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	5.203m	1.599ms	1	1	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	5.203m	1.599ms	1	1	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	3.580s	327.784us	1	1	100.00
V2S	sec_cm_prim_ram_ctrl_mubi	sram_ctrl_mubi_enc_err	1.090s	435.163us	1	1	100.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	2.190s	372.174us	1	1	100.00
V2S	sec_cm_mem_readback	sram_ctrl_readback_err	0.890s	190.460us	1	1	100.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	10.790s	2.656ms	1	1	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	10.790s	2.656ms	1	1	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	5.203m	1.599ms	1	1	100.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	0.630s	14.312us	0	1	0.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	3.580s	327.784us	1	1	100.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	0.630s	14.312us	0	1	0.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	0.630s	14.312us	0	1	0.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	10.790s	2.656ms	1	1	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	0.630s	14.312us	0	1	0.00
V2S		TOTAL			4	5	80.00
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	2.118m	2.056ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			30	31	96.77

Failure Buckets

• UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: * has 1 failures:
  • Test sram_ctrl_sec_cm has 1 failures.

    • 0.sram_ctrl_sec_cm.84433813583836523627745250616577348242787609086881726886744699376539473383671
      Line 97, in log /nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/0.sram_ctrl_sec_cm/latest/run.log

        UVM_ERROR @  14311967 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0
        UVM_INFO @  14311967 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---