SYSRST_CTRL Simulation Results

Thursday October 09 2025 19:22:42 UTC

GitHub Revision: 677ee3d

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke sysrst_ctrl_smoke 1.600s 2.125ms 1 1 100.00
V1 input_output_inverted sysrst_ctrl_in_out_inverted 1.760s 2.480ms 1 1 100.00
V1 combo_detect_ec_rst sysrst_ctrl_combo_detect_ec_rst 5.020s 2.429ms 1 1 100.00
V1 combo_detect_ec_rst_with_pre_cond sysrst_ctrl_combo_detect_ec_rst_with_pre_cond 2.190s 2.535ms 1 1 100.00
V1 csr_hw_reset sysrst_ctrl_csr_hw_reset 2.860s 4.046ms 1 1 100.00
V1 csr_rw sysrst_ctrl_csr_rw 2.520s 2.044ms 1 1 100.00
V1 csr_bit_bash sysrst_ctrl_csr_bit_bash 7.980s 10.220ms 1 1 100.00
V1 csr_aliasing sysrst_ctrl_csr_aliasing 6.680s 2.413ms 1 1 100.00
V1 csr_mem_rw_with_rand_reset sysrst_ctrl_csr_mem_rw_with_rand_reset 1.210s 2.186ms 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr sysrst_ctrl_csr_rw 2.520s 2.044ms 1 1 100.00
sysrst_ctrl_csr_aliasing 6.680s 2.413ms 1 1 100.00
V1 TOTAL 9 9 100.00
V2 combo_detect sysrst_ctrl_combo_detect 1.008m 125.555ms 1 1 100.00
V2 combo_detect_with_pre_cond sysrst_ctrl_combo_detect_with_pre_cond 1.431m 48.191ms 1 1 100.00
V2 auto_block_key_outputs sysrst_ctrl_auto_blk_key_output 1.120s 3.832ms 1 1 100.00
V2 keyboard_input_triggered_interrupt sysrst_ctrl_edge_detect 6.090s 2.937ms 1 1 100.00
V2 pin_output_keyboard_inversion_control sysrst_ctrl_pin_override_test 5.460s 2.509ms 1 1 100.00
V2 pin_input_value_accessibility sysrst_ctrl_pin_access_test 1.700s 2.193ms 1 1 100.00
V2 ec_power_on_reset sysrst_ctrl_ec_pwr_on_rst 5.040s 4.518ms 1 1 100.00
V2 flash_write_protect_output sysrst_ctrl_flash_wr_prot_out 2.950s 2.614ms 1 1 100.00
V2 ultra_low_power_test sysrst_ctrl_ultra_low_pwr 5.690s 5.445ms 1 1 100.00
V2 sysrst_ctrl_feature_disable sysrst_ctrl_feature_disable 15.410s 30.408ms 1 1 100.00
V2 stress_all sysrst_ctrl_stress_all 14.440s 13.501ms 1 1 100.00
V2 alert_test sysrst_ctrl_alert_test 5.480s 2.013ms 1 1 100.00
V2 intr_test sysrst_ctrl_intr_test 1.690s 2.038ms 1 1 100.00
V2 tl_d_oob_addr_access sysrst_ctrl_tl_errors 5.420s 2.038ms 1 1 100.00
V2 tl_d_illegal_access sysrst_ctrl_tl_errors 5.420s 2.038ms 1 1 100.00
V2 tl_d_outstanding_access sysrst_ctrl_csr_hw_reset 2.860s 4.046ms 1 1 100.00
sysrst_ctrl_csr_rw 2.520s 2.044ms 1 1 100.00
sysrst_ctrl_csr_aliasing 6.680s 2.413ms 1 1 100.00
sysrst_ctrl_same_csr_outstanding 6.460s 4.577ms 1 1 100.00
V2 tl_d_partial_access sysrst_ctrl_csr_hw_reset 2.860s 4.046ms 1 1 100.00
sysrst_ctrl_csr_rw 2.520s 2.044ms 1 1 100.00
sysrst_ctrl_csr_aliasing 6.680s 2.413ms 1 1 100.00
sysrst_ctrl_same_csr_outstanding 6.460s 4.577ms 1 1 100.00
V2 TOTAL 15 15 100.00
V2S tl_intg_err sysrst_ctrl_sec_cm 22.220s 42.124ms 1 1 100.00
sysrst_ctrl_tl_intg_err 23.270s 42.920ms 1 1 100.00
V2S sec_cm_bus_integrity sysrst_ctrl_tl_intg_err 23.270s 42.920ms 1 1 100.00
V2S TOTAL 2 2 100.00
V3 stress_all_with_rand_reset sysrst_ctrl_stress_all_with_rand_reset 9.990s 4.561ms 1 1 100.00
V3 TOTAL 1 1 100.00
TOTAL 27 27 100.00