UART Simulation Results

Thursday October 09 2025 19:22:42 UTC

GitHub Revision: 677ee3d

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	uart_smoke	1.900s	737.727us	1	1	100.00
V1	csr_hw_reset	uart_csr_hw_reset	0.700s	16.329us	1	1	100.00
V1	csr_rw	uart_csr_rw	0.680s	16.619us	1	1	100.00
V1	csr_bit_bash	uart_csr_bit_bash	1.290s	35.364us	1	1	100.00
V1	csr_aliasing	uart_csr_aliasing	0.750s	23.447us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	uart_csr_mem_rw_with_rand_reset	1.850s	166.983us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	uart_csr_rw	0.680s	16.619us	1	1	100.00
		uart_csr_aliasing	0.750s	23.447us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	base_random_seq	uart_tx_rx	35.280s	67.071ms	1	1	100.00
V2	parity	uart_smoke	1.900s	737.727us	1	1	100.00
		uart_tx_rx	35.280s	67.071ms	1	1	100.00
V2	parity_error	uart_intr	32.270s	102.030ms	1	1	100.00
		uart_rx_parity_err	44.980s	84.120ms	1	1	100.00
V2	watermark	uart_tx_rx	35.280s	67.071ms	1	1	100.00
		uart_intr	32.270s	102.030ms	1	1	100.00
V2	fifo_full	uart_fifo_full	24.200s	128.113ms	1	1	100.00
V2	fifo_overflow	uart_fifo_overflow	35.120s	28.650ms	1	1	100.00
V2	fifo_reset	uart_fifo_reset	29.270s	32.961ms	1	1	100.00
V2	rx_frame_err	uart_intr	32.270s	102.030ms	1	1	100.00
V2	rx_break_err	uart_intr	32.270s	102.030ms	1	1	100.00
V2	rx_timeout	uart_intr	32.270s	102.030ms	1	1	100.00
V2	perf	uart_perf	11.000m	22.427ms	1	1	100.00
V2	sys_loopback	uart_loopback	17.310s	10.894ms	1	1	100.00
V2	line_loopback	uart_loopback	17.310s	10.894ms	1	1	100.00
V2	rx_noise_filter	uart_noise_filter	15.380s	39.206ms	0	1	0.00
V2	rx_start_bit_filter	uart_rx_start_bit_filter	2.200s	5.572ms	1	1	100.00
V2	tx_overide	uart_tx_ovrd	10.050s	7.560ms	1	1	100.00
V2	rx_oversample	uart_rx_oversample	6.750s	4.036ms	1	1	100.00
V2	long_b2b_transfer	uart_long_xfer_wo_dly	1.630m	114.934ms	1	1	100.00
V2	stress_all	uart_stress_all	3.667m	176.254ms	1	1	100.00
V2	alert_test	uart_alert_test	0.580s	15.966us	1	1	100.00
V2	intr_test	uart_intr_test	0.720s	16.721us	1	1	100.00
V2	tl_d_oob_addr_access	uart_tl_errors	1.610s	211.124us	1	1	100.00
V2	tl_d_illegal_access	uart_tl_errors	1.610s	211.124us	1	1	100.00
V2	tl_d_outstanding_access	uart_csr_hw_reset	0.700s	16.329us	1	1	100.00
		uart_csr_rw	0.680s	16.619us	1	1	100.00
		uart_csr_aliasing	0.750s	23.447us	1	1	100.00
		uart_same_csr_outstanding	0.840s	16.018us	1	1	100.00
V2	tl_d_partial_access	uart_csr_hw_reset	0.700s	16.329us	1	1	100.00
		uart_csr_rw	0.680s	16.619us	1	1	100.00
		uart_csr_aliasing	0.750s	23.447us	1	1	100.00
		uart_same_csr_outstanding	0.840s	16.018us	1	1	100.00
V2		TOTAL			17	18	94.44
V2S	tl_intg_err	uart_sec_cm	0.840s	167.853us	1	1	100.00
		uart_tl_intg_err	0.820s	48.177us	1	1	100.00
V2S	sec_cm_bus_integrity	uart_tl_intg_err	0.820s	48.177us	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	stress_all_with_rand_reset	uart_stress_all_with_rand_reset	39.720s	18.154ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			26	27	96.30

Failure Buckets

• UVM_ERROR (uart_scoreboard.sv:393) [scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (* [*] vs * [*]) check rx_idle fail: rx_en = *, uart_rx_clk_pulses = * has 1 failures:
  • Test uart_noise_filter has 1 failures.

    • 0.uart_noise_filter.108293850258490469943968016054254544044906699467517400314503596464192306752391
      Line 72, in log /nightly/current_run/scratch/master/uart-sim-vcs/0.uart_noise_filter/latest/run.log

        UVM_ERROR @ 36298313084 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
        UVM_ERROR @ 36604773869 ps: (uart_scoreboard.sv:377) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (0 [0x0] vs 1 [0x1]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 0
        UVM_ERROR @ 36604773869 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
        UVM_ERROR @ 36604773869 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1
        UVM_ERROR @ 36818900582 ps: (uart_scoreboard.sv:501) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 1 (+/-1), act: 2,                                 clk_pulses: 0