CHIP Simulation Results

Thursday October 09 2025 19:22:42 UTC

GitHub Revision: `677ee3d`

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	chip_sw_example_tests	chip_sw_example_flash	2.268m	2.196ms	1	1	100.00
		chip_sw_example_rom	54.490s	2.578ms	1	1	100.00
		chip_sw_example_manufacturer	1.918m	3.061ms	1	1	100.00
		chip_sw_example_concurrency	2.637m	3.058ms	1	1	100.00
V1	csr_hw_reset	chip_csr_hw_reset	4.340m	6.688ms	1	1	100.00
V1	csr_rw	chip_csr_rw	3.117m	4.668ms	1	1	100.00
V1	csr_bit_bash	chip_csr_bit_bash	37.981m	31.718ms	1	1	100.00
V1	csr_aliasing	chip_csr_aliasing	1.016h	28.672ms	1	1	100.00
V1	csr_mem_rw_with_rand_reset	chip_csr_mem_rw_with_rand_reset	49.430s	1.954ms	0	1	0.00
V1	regwen_csr_and_corresponding_lockable_csr	chip_csr_aliasing	1.016h	28.672ms	1	1	100.00
		chip_csr_rw	3.117m	4.668ms	1	1	100.00
V1	xbar_smoke	xbar_smoke	5.300s	43.706us	1	1	100.00
V1	chip_sw_gpio_out	chip_sw_gpio	5.533m	4.067ms	1	1	100.00
V1	chip_sw_gpio_in	chip_sw_gpio	5.533m	4.067ms	1	1	100.00
V1	chip_sw_gpio_irq	chip_sw_gpio	5.533m	4.067ms	1	1	100.00
V1	chip_sw_uart_tx_rx	chip_sw_uart_tx_rx	6.236m	3.766ms	1	1	100.00
V1	chip_sw_uart_rx_overflow	chip_sw_uart_tx_rx	6.236m	3.766ms	1	1	100.00
		chip_sw_uart_tx_rx_idx1	5.974m	3.791ms	1	1	100.00
		chip_sw_uart_tx_rx_idx2	6.170m	3.523ms	1	1	100.00
		chip_sw_uart_tx_rx_idx3	6.372m	4.178ms	1	1	100.00
V1	chip_sw_uart_baud_rate	chip_sw_uart_rand_baudrate	28.198m	13.483ms	1	1	100.00
V1	chip_sw_uart_tx_rx_alt_clk_freq	chip_sw_uart_tx_rx_alt_clk_freq	16.392m	7.952ms	1	1	100.00
		chip_sw_uart_tx_rx_alt_clk_freq_low_speed	18.053m	13.061ms	1	1	100.00
V1		TOTAL			17	18	94.44
V2	chip_pin_mux	chip_padctrl_attributes	3.070m	5.023ms	1	1	100.00
V2	chip_padctrl_attributes	chip_padctrl_attributes	3.070m	5.023ms	1	1	100.00
V2	chip_sw_sleep_pin_mio_dio_val	chip_sw_sleep_pin_mio_dio_val	2.526m	3.219ms	0	1	0.00
V2	chip_sw_sleep_pin_wake	chip_sw_sleep_pin_wake	3.615m	5.005ms	1	1	100.00
V2	chip_sw_sleep_pin_retention	chip_sw_sleep_pin_retention	2.537m	3.457ms	1	1	100.00
V2	chip_sw_tap_strap_sampling	chip_tap_straps_dev	18.738m	17.695ms	1	1	100.00
		chip_tap_straps_testunlock0	3.094m	3.767ms	1	1	100.00
		chip_tap_straps_rma	6.021m	6.193ms	1	1	100.00
		chip_tap_straps_prod	1.733m	2.752ms	1	1	100.00
V2	chip_sw_pattgen_ios	chip_sw_pattgen_ios	2.288m	2.838ms	1	1	100.00
V2	chip_sw_sleep_pwm_pulses	chip_sw_sleep_pwm_pulses	12.133m	8.163ms	1	1	100.00
V2	chip_sw_data_integrity	chip_sw_data_integrity_escalation	9.004m	5.516ms	1	1	100.00
V2	chip_sw_instruction_integrity	chip_sw_data_integrity_escalation	9.004m	5.516ms	1	1	100.00
V2	chip_sw_ast_clk_outputs	chip_sw_ast_clk_outputs	9.519m	7.964ms	1	1	100.00
V2	chip_sw_ast_clk_rst_inputs	chip_sw_ast_clk_rst_inputs	39.500m	22.426ms	0	1	0.00
V2	chip_sw_ast_sys_clk_jitter	chip_sw_flash_ctrl_ops_jitter_en	5.744m	3.997ms	1	1	100.00
		chip_sw_flash_ctrl_access_jitter_en	10.656m	6.391ms	1	1	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en	55.655m	19.085ms	1	1	100.00
		chip_sw_aes_enc_jitter_en	2.662m	3.237ms	1	1	100.00
		chip_sw_edn_entropy_reqs_jitter	10.672m	6.615ms	1	1	100.00
		chip_sw_hmac_enc_jitter_en	2.580m	2.676ms	1	1	100.00
		chip_sw_keymgr_key_derivation_jitter_en	9.661m	7.182ms	1	1	100.00
		chip_sw_kmac_mode_kmac_jitter_en	3.641m	3.356ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	4.499m	3.711ms	1	1	100.00
		chip_sw_clkmgr_jitter	1.620m	2.671ms	1	1	100.00
V2	chip_sw_ast_usb_clk_calib	chip_sw_usb_ast_clk_calib	3.354m	3.457ms	1	1	100.00
V2	chip_sw_sensor_ctrl_ast_alerts	chip_sw_sensor_ctrl_alert	7.223m	5.050ms	1	1	100.00
		chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	3.964m	5.394ms	1	1	100.00
V2	chip_sw_sensor_ctrl_ast_status	chip_sw_sensor_ctrl_status	2.234m	2.398ms	1	1	100.00
V2	chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	3.964m	5.394ms	1	1	100.00
V2	chip_sw_smoketest	chip_sw_flash_scrambling_smoketest	2.767m	3.545ms	1	1	100.00
		chip_sw_aes_smoketest	2.371m	2.559ms	1	1	100.00
		chip_sw_aon_timer_smoketest	2.502m	2.889ms	1	1	100.00
		chip_sw_clkmgr_smoketest	2.725m	2.732ms	1	1	100.00
		chip_sw_csrng_smoketest	2.230m	3.010ms	1	1	100.00
		chip_sw_entropy_src_smoketest	12.983m	7.123ms	1	1	100.00
		chip_sw_gpio_smoketest	2.502m	3.142ms	1	1	100.00
		chip_sw_hmac_smoketest	3.568m	3.893ms	1	1	100.00
		chip_sw_kmac_smoketest	2.585m	2.753ms	1	1	100.00
		chip_sw_otbn_smoketest	18.514m	9.664ms	1	1	100.00
		chip_sw_pwrmgr_smoketest	4.699m	6.040ms	1	1	100.00
		chip_sw_pwrmgr_usbdev_smoketest	4.050m	5.858ms	1	1	100.00
		chip_sw_rv_plic_smoketest	2.974m	3.184ms	1	1	100.00
		chip_sw_rv_timer_smoketest	1.697m	2.766ms	1	1	100.00
		chip_sw_rstmgr_smoketest	2.905m	2.948ms	1	1	100.00
		chip_sw_sram_ctrl_smoketest	1.859m	2.411ms	1	1	100.00
		chip_sw_uart_smoketest	2.124m	3.013ms	1	1	100.00
V2	chip_sw_otp_smoketest	chip_sw_otp_ctrl_smoketest	2.386m	2.102ms	1	1	100.00
V2	chip_sw_rom_functests	rom_keymgr_functest	4.176m	4.226ms	1	1	100.00
V2	chip_sw_boot	chip_sw_uart_tx_rx_bootstrap	2.169h	60.615ms	1	1	100.00
V2	chip_sw_secure_boot	rom_e2e_smoke	42.726m	14.612ms	1	1	100.00
V2	chip_sw_rom_raw_unlock	rom_raw_unlock	2.730m	5.982ms	1	1	100.00
V2	chip_sw_power_idle_load	chip_sw_power_idle_load	3.206m	3.369ms	0	1	0.00
V2	chip_sw_power_sleep_load	chip_sw_power_sleep_load	2.973m	3.083ms	0	1	0.00
V2	chip_sw_exit_test_unlocked_bootstrap	chip_sw_exit_test_unlocked_bootstrap	1.941h	53.991ms	1	1	100.00
V2	chip_sw_inject_scramble_seed	chip_sw_inject_scramble_seed	2.097h	56.411ms	1	1	100.00
V2	tl_d_oob_addr_access	chip_tl_errors	55.740s	2.912ms	0	1	0.00
V2	tl_d_illegal_access	chip_tl_errors	55.740s	2.912ms	0	1	0.00
V2	tl_d_outstanding_access	chip_csr_aliasing	1.016h	28.672ms	1	1	100.00
		chip_same_csr_outstanding	48.219m	29.546ms	1	1	100.00
		chip_csr_hw_reset	4.340m	6.688ms	1	1	100.00
		chip_csr_rw	3.117m	4.668ms	1	1	100.00
V2	tl_d_partial_access	chip_csr_aliasing	1.016h	28.672ms	1	1	100.00
		chip_same_csr_outstanding	48.219m	29.546ms	1	1	100.00
		chip_csr_hw_reset	4.340m	6.688ms	1	1	100.00
		chip_csr_rw	3.117m	4.668ms	1	1	100.00
V2	xbar_base_random_sequence	xbar_random	20.220s	371.352us	1	1	100.00
V2	xbar_random_delay	xbar_smoke_zero_delays	5.190s	44.402us	1	1	100.00
		xbar_smoke_large_delays	1.068m	10.487ms	1	1	100.00
		xbar_smoke_slow_rsp	46.260s	5.336ms	1	1	100.00
		xbar_random_zero_delays	32.690s	577.432us	1	1	100.00
		xbar_random_large_delays	5.229m	51.559ms	1	1	100.00
		xbar_random_slow_rsp	30.780s	3.429ms	1	1	100.00
V2	xbar_unmapped_address	xbar_unmapped_addr	6.770s	68.957us	1	1	100.00
		xbar_error_and_unmapped_addr	34.820s	1.291ms	1	1	100.00
V2	xbar_error_cases	xbar_error_random	23.800s	1.017ms	1	1	100.00
		xbar_error_and_unmapped_addr	34.820s	1.291ms	1	1	100.00
V2	xbar_all_access_same_device	xbar_access_same_device	1.302m	3.209ms	1	1	100.00
		xbar_access_same_device_slow_rsp	11.356m	77.733ms	1	1	100.00
V2	xbar_all_hosts_use_same_source_id	xbar_same_source	19.500s	418.960us	1	1	100.00
V2	xbar_stress_all	xbar_stress_all	4.213m	11.300ms	1	1	100.00
		xbar_stress_all_with_error	2.966m	9.309ms	1	1	100.00
V2	xbar_stress_with_reset	xbar_stress_all_with_rand_reset	1.201m	385.283us	1	1	100.00
		xbar_stress_all_with_reset_error	2.038m	3.127ms	1	1	100.00
V2	rom_e2e_smoke	rom_e2e_smoke	42.726m	14.612ms	1	1	100.00
V2	rom_e2e_shutdown_output	rom_e2e_shutdown_output	36.794m	29.114ms	1	1	100.00
V2	rom_e2e_shutdown_exception_c	rom_e2e_shutdown_exception_c	43.464m	15.686ms	1	1	100.00
V2	rom_e2e_boot_policy_valid	rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0	33.436m	12.698ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_dev	43.883m	17.880ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod	41.837m	15.816ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod_end	41.834m	17.062ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_rma	40.716m	14.933ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0	17.360s	10.100us	0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_dev	17.450s	10.360us	0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod	20.000s	10.400us	0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod_end	17.560s	10.280us	0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_rma	17.630s	10.140us	0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0	17.280s	10.320us	0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_dev	16.910s	10.160us	0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod	29.380s	10.340us	0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod_end	16.690s	10.320us	0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_rma	17.690s	10.280us	0	1	0.00
V2	rom_e2e_sigverify_always	rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0	16.380s	10.240us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_dev	16.890s	10.200us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod	16.810s	10.340us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod_end	24.880s	10.120us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_rma	21.310s	10.120us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0	16.430s	10.200us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_dev	16.390s	10.300us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod	17.980s	10.240us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod_end	16.550s	10.320us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_rma	16.250s	10.220us	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0	16.440s	10.140us	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_dev	17.210s	10.380us	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod	16.760s	10.120us	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod_end	16.150s	10.280us	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_rma	16.380s	10.220us	0	1	0.00
V2	rom_e2e_asm_init	rom_e2e_asm_init_test_unlocked0	31.710m	11.192ms	1	1	100.00
		rom_e2e_asm_init_dev	43.013m	15.715ms	1	1	100.00
		rom_e2e_asm_init_prod	42.270m	16.876ms	1	1	100.00
		rom_e2e_asm_init_prod_end	40.363m	15.640ms	1	1	100.00
		rom_e2e_asm_init_rma	39.355m	15.612ms	1	1	100.00
V2	rom_e2e_keymgr_init	rom_e2e_keymgr_init_rom_ext_meas	39.681m	15.002ms	1	1	100.00
		rom_e2e_keymgr_init_rom_ext_no_meas	38.755m	14.812ms	1	1	100.00
		rom_e2e_keymgr_init_rom_ext_invalid_meas	40.896m	14.695ms	1	1	100.00
V2	rom_e2e_static_critical	rom_e2e_static_critical	41.497m	17.138ms	1	1	100.00
V2	chip_sw_adc_ctrl_debug_cable_irq	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	54.287m	34.876ms	0	1	0.00
V2	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	54.287m	34.876ms	0	1	0.00
V2	chip_sw_aes_enc	chip_sw_aes_enc	3.437m	3.512ms	1	1	100.00
		chip_sw_aes_enc_jitter_en	2.662m	3.237ms	1	1	100.00
V2	chip_sw_aes_entropy	chip_sw_aes_entropy	2.031m	2.684ms	1	1	100.00
V2	chip_sw_aes_idle	chip_sw_aes_idle	1.979m	2.677ms	1	1	100.00
V2	chip_sw_aes_sideload	chip_sw_keymgr_sideload_aes	18.091m	8.811ms	1	1	100.00
V2	chip_sw_alert_handler_alerts	chip_sw_alert_test	3.081m	2.964ms	0	1	0.00
V2	chip_sw_alert_handler_escalations	chip_sw_alert_handler_escalation	5.125m	5.958ms	1	1	100.00
V2	chip_sw_all_escalation_resets	chip_sw_all_escalation_resets	6.014m	4.893ms	1	1	100.00
V2	chip_sw_alert_handler_irqs	chip_plic_all_irqs_0	9.394m	5.331ms	1	1	100.00
		chip_plic_all_irqs_10	4.252m	3.600ms	1	1	100.00
		chip_plic_all_irqs_20	6.268m	3.738ms	1	1	100.00
V2	chip_sw_alert_handler_entropy	chip_sw_alert_handler_entropy	3.035m	3.541ms	1	1	100.00
V2	chip_sw_alert_handler_crashdump	chip_sw_rstmgr_alert_info	19.352m	12.019ms	1	1	100.00
V2	chip_sw_alert_handler_ping_timeout	chip_sw_alert_handler_ping_timeout	3.665m	3.497ms	1	1	100.00
V2	chip_sw_alert_handler_lpg_sleep_mode_alerts	chip_sw_alert_handler_lpg_sleep_mode_alerts	2.372m	3.290ms	0	1	0.00
V2	chip_sw_alert_handler_lpg_sleep_mode_pings	chip_sw_alert_handler_lpg_sleep_mode_pings			0	1	0.00
V2	chip_sw_alert_handler_lpg_clock_off	chip_sw_alert_handler_lpg_clkoff	14.662m	7.169ms	1	1	100.00
V2	chip_sw_alert_handler_lpg_reset_toggle	chip_sw_alert_handler_lpg_reset_toggle	18.849m	7.761ms	1	1	100.00
V2	chip_sw_alert_handler_ping_ok	chip_sw_alert_handler_ping_ok	14.187m	8.382ms	1	1	100.00
V2	chip_sw_alert_handler_reverse_ping_in_deep_sleep	chip_sw_alert_handler_reverse_ping_in_deep_sleep	2.055h	255.540ms	1	1	100.00
V2	chip_sw_aon_timer_wakeup_irq	chip_sw_aon_timer_irq	4.095m	4.494ms	1	1	100.00
V2	chip_sw_aon_timer_sleep_wakeup	chip_sw_pwrmgr_smoketest	4.699m	6.040ms	1	1	100.00
V2	chip_sw_aon_timer_wdog_bark_irq	chip_sw_aon_timer_irq	4.095m	4.494ms	1	1	100.00
V2	chip_sw_aon_timer_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	7.606m	7.731ms	1	1	100.00
V2	chip_sw_aon_timer_sleep_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	7.606m	7.731ms	1	1	100.00
V2	chip_sw_aon_timer_sleep_wdog_sleep_pause	chip_sw_aon_timer_sleep_wdog_sleep_pause	3.769m	6.173ms	1	1	100.00
V2	chip_sw_aon_timer_wdog_lc_escalate	chip_sw_aon_timer_wdog_lc_escalate	6.852m	5.422ms	1	1	100.00
V2	chip_sw_clkmgr_idle_trans	chip_sw_otbn_randomness	9.775m	5.677ms	1	1	100.00
		chip_sw_aes_idle	1.979m	2.677ms	1	1	100.00
		chip_sw_hmac_enc_idle	2.668m	3.315ms	1	1	100.00
		chip_sw_kmac_idle	2.593m	2.514ms	1	1	100.00
V2	chip_sw_clkmgr_off_trans	chip_sw_clkmgr_off_aes_trans	3.524m	4.855ms	1	1	100.00
		chip_sw_clkmgr_off_hmac_trans	4.163m	4.461ms	1	1	100.00
		chip_sw_clkmgr_off_kmac_trans	4.899m	4.785ms	1	1	100.00
		chip_sw_clkmgr_off_otbn_trans	5.155m	4.683ms	1	1	100.00
V2	chip_sw_clkmgr_off_peri	chip_sw_clkmgr_off_peri	12.393m	10.810ms	1	1	100.00
V2	chip_sw_clkmgr_div	chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	6.240m	4.026ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	6.351m	4.496ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	6.475m	3.800ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	6.499m	5.068ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	5.962m	4.161ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	6.630m	4.913ms	1	1	100.00
		chip_sw_ast_clk_outputs	9.519m	7.964ms	1	1	100.00
V2	chip_sw_clkmgr_external_clk_src_for_lc	chip_sw_clkmgr_external_clk_src_for_lc	5.932m	6.742ms	1	1	100.00
V2	chip_sw_clkmgr_external_clk_src_for_sw	chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	6.475m	3.800ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	6.499m	5.068ms	1	1	100.00
V2	chip_sw_clkmgr_jitter	chip_sw_flash_ctrl_ops_jitter_en	5.744m	3.997ms	1	1	100.00
		chip_sw_flash_ctrl_access_jitter_en	10.656m	6.391ms	1	1	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en	55.655m	19.085ms	1	1	100.00
		chip_sw_aes_enc_jitter_en	2.662m	3.237ms	1	1	100.00
		chip_sw_edn_entropy_reqs_jitter	10.672m	6.615ms	1	1	100.00
		chip_sw_hmac_enc_jitter_en	2.580m	2.676ms	1	1	100.00
		chip_sw_keymgr_key_derivation_jitter_en	9.661m	7.182ms	1	1	100.00
		chip_sw_kmac_mode_kmac_jitter_en	3.641m	3.356ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	4.499m	3.711ms	1	1	100.00
		chip_sw_clkmgr_jitter	1.620m	2.671ms	1	1	100.00
V2	chip_sw_clkmgr_extended_range	chip_sw_clkmgr_jitter_reduced_freq	2.852m	3.260ms	1	1	100.00
		chip_sw_flash_ctrl_ops_jitter_en_reduced_freq	6.816m	4.874ms	1	1	100.00
		chip_sw_flash_ctrl_access_jitter_en_reduced_freq	10.213m	7.619ms	1	1	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq	49.816m	24.642ms	1	1	100.00
		chip_sw_aes_enc_jitter_en_reduced_freq	2.380m	3.157ms	1	1	100.00
		chip_sw_hmac_enc_jitter_en_reduced_freq	2.594m	3.307ms	1	1	100.00
		chip_sw_keymgr_key_derivation_jitter_en_reduced_freq	9.911m	6.920ms	1	1	100.00
		chip_sw_kmac_mode_kmac_jitter_en_reduced_freq	2.896m	2.832ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq	6.185m	5.805ms	1	1	100.00
		chip_sw_flash_init_reduced_freq	19.836m	23.595ms	1	1	100.00
		chip_sw_csrng_edn_concurrency_reduced_freq	31.021m	16.469ms	1	1	100.00
V2	chip_sw_clkmgr_deep_sleep_frequency	chip_sw_ast_clk_outputs	9.519m	7.964ms	1	1	100.00
V2	chip_sw_clkmgr_sleep_frequency	chip_sw_clkmgr_sleep_frequency	6.123m	4.520ms	1	1	100.00
V2	chip_sw_clkmgr_reset_frequency	chip_sw_clkmgr_reset_frequency	4.357m	3.421ms	1	1	100.00
V2	chip_sw_clkmgr_escalation_reset	chip_sw_all_escalation_resets	6.014m	4.893ms	1	1	100.00
V2	chip_sw_clkmgr_alert_handler_clock_enables	chip_sw_alert_handler_lpg_clkoff	14.662m	7.169ms	1	1	100.00
V2	chip_sw_csrng_edn_cmd	chip_sw_entropy_src_csrng	15.948m	7.312ms	1	1	100.00
V2	chip_sw_csrng_fuse_en_sw_app_read	chip_sw_csrng_fuse_en_sw_app_read_test	4.045m	4.375ms	1	1	100.00
V2	chip_sw_csrng_lc_hw_debug_en	chip_sw_csrng_lc_hw_debug_en_test	4.898m	5.204ms	1	1	100.00
V2	chip_sw_csrng_known_answer_tests	chip_sw_csrng_kat_test	2.413m	2.937ms	1	1	100.00
V2	chip_sw_edn_entropy_reqs	chip_sw_csrng_edn_concurrency	1.085h	23.850ms	1	1	100.00
		chip_sw_entropy_src_ast_rng_req	1.859m	2.948ms	1	1	100.00
		chip_sw_edn_entropy_reqs	13.994m	7.364ms	1	1	100.00
V2	chip_sw_entropy_src_ast_rng_req	chip_sw_entropy_src_ast_rng_req	1.859m	2.948ms	1	1	100.00
V2	chip_sw_entropy_src_csrng	chip_sw_entropy_src_csrng	15.948m	7.312ms	1	1	100.00
V2	chip_sw_entropy_src_known_answer_tests	chip_sw_entropy_src_kat_test	2.305m	2.609ms	1	1	100.00
V2	chip_sw_flash_init	chip_sw_flash_init	21.377m	22.755ms	1	1	100.00
V2	chip_sw_flash_host_access	chip_sw_flash_ctrl_access	9.546m	5.530ms	1	1	100.00
		chip_sw_flash_ctrl_access_jitter_en	10.656m	6.391ms	1	1	100.00
V2	chip_sw_flash_ctrl_ops	chip_sw_flash_ctrl_ops	5.332m	4.250ms	1	1	100.00
		chip_sw_flash_ctrl_ops_jitter_en	5.744m	3.997ms	1	1	100.00
V2	chip_sw_flash_rma_unlocked	chip_sw_flash_rma_unlocked	1.052h	43.752ms	1	1	100.00
V2	chip_sw_flash_scramble	chip_sw_flash_init	21.377m	22.755ms	1	1	100.00
V2	chip_sw_flash_idle_low_power	chip_sw_flash_ctrl_idle_low_power	2.941m	2.861ms	1	1	100.00
V2	chip_sw_flash_keymgr_seeds	chip_sw_keymgr_key_derivation	13.555m	6.485ms	1	1	100.00
V2	chip_sw_flash_lc_creator_seed_sw_rw_en	chip_sw_flash_ctrl_lc_rw_en	4.310m	4.593ms	1	1	100.00
V2	chip_sw_flash_creator_seed_wipe_on_rma	chip_sw_flash_rma_unlocked	1.052h	43.752ms	1	1	100.00
V2	chip_sw_flash_lc_owner_seed_sw_rw_en	chip_sw_flash_ctrl_lc_rw_en	4.310m	4.593ms	1	1	100.00
V2	chip_sw_flash_lc_iso_part_sw_rd_en	chip_sw_flash_ctrl_lc_rw_en	4.310m	4.593ms	1	1	100.00
V2	chip_sw_flash_lc_iso_part_sw_wr_en	chip_sw_flash_ctrl_lc_rw_en	4.310m	4.593ms	1	1	100.00
V2	chip_sw_flash_lc_seed_hw_rd_en	chip_sw_flash_ctrl_lc_rw_en	4.310m	4.593ms	1	1	100.00
V2	chip_sw_flash_lc_escalate_en	chip_sw_all_escalation_resets	6.014m	4.893ms	1	1	100.00
V2	chip_sw_flash_prim_tl_access	chip_prim_tl_access	2.533m	6.501ms	1	1	100.00
V2	chip_sw_flash_ctrl_clock_freqs	chip_sw_flash_ctrl_clock_freqs	9.912m	5.334ms	1	1	100.00
V2	chip_sw_flash_ctrl_escalation_reset	chip_sw_flash_crash_alert	6.292m	5.176ms	1	1	100.00
V2	chip_sw_flash_ctrl_write_clear	chip_sw_flash_crash_alert	6.292m	5.176ms	1	1	100.00
V2	chip_sw_hmac_enc	chip_sw_hmac_enc	2.930m	3.108ms	1	1	100.00
		chip_sw_hmac_enc_jitter_en	2.580m	2.676ms	1	1	100.00
V2	chip_sw_hmac_idle	chip_sw_hmac_enc_idle	2.668m	3.315ms	1	1	100.00
V2	chip_sw_hmac_all_configurations	chip_sw_hmac_oneshot	2.430m	3.087ms	0	1	0.00
V2	chip_sw_hmac_multistream_mode	chip_sw_hmac_multistream	5.739m	4.317ms	1	1	100.00
V2	chip_sw_i2c_host_tx_rx	chip_sw_i2c_host_tx_rx	7.586m	4.919ms	1	1	100.00
		chip_sw_i2c_host_tx_rx_idx1	7.391m	4.945ms	1	1	100.00
		chip_sw_i2c_host_tx_rx_idx2	5.075m	4.582ms	1	1	100.00
V2	chip_sw_i2c_device_tx_rx	chip_sw_i2c_device_tx_rx	5.769m	4.104ms	1	1	100.00
V2	chip_sw_keymgr_key_derivation	chip_sw_keymgr_key_derivation	13.555m	6.485ms	1	1	100.00
		chip_sw_keymgr_key_derivation_jitter_en	9.661m	7.182ms	1	1	100.00
V2	chip_sw_keymgr_sideload_kmac	chip_sw_keymgr_sideload_kmac	15.635m	8.497ms	1	1	100.00
V2	chip_sw_keymgr_sideload_aes	chip_sw_keymgr_sideload_aes	18.091m	8.811ms	1	1	100.00
V2	chip_sw_keymgr_sideload_otbn	chip_sw_keymgr_sideload_otbn	44.929m	14.074ms	1	1	100.00
V2	chip_sw_kmac_enc	chip_sw_kmac_mode_cshake	2.252m	2.808ms	1	1	100.00
		chip_sw_kmac_mode_kmac	2.778m	2.720ms	1	1	100.00
		chip_sw_kmac_mode_kmac_jitter_en	3.641m	3.356ms	1	1	100.00
V2	chip_sw_kmac_app_keymgr	chip_sw_keymgr_key_derivation	13.555m	6.485ms	1	1	100.00
V2	chip_sw_kmac_app_lc	chip_sw_lc_ctrl_transition	7.405m	11.569ms	1	1	100.00
V2	chip_sw_kmac_app_rom	chip_sw_kmac_app_rom	2.644m	2.444ms	1	1	100.00
V2	chip_sw_kmac_entropy	chip_sw_kmac_entropy	28.173m	11.232ms	1	1	100.00
V2	chip_sw_kmac_idle	chip_sw_kmac_idle	2.593m	2.514ms	1	1	100.00
V2	chip_sw_lc_ctrl_alert_handler_escalation	chip_sw_alert_handler_escalation	5.125m	5.958ms	1	1	100.00
V2	chip_sw_lc_ctrl_jtag_access	chip_tap_straps_dev	18.738m	17.695ms	1	1	100.00
		chip_tap_straps_rma	6.021m	6.193ms	1	1	100.00
		chip_tap_straps_prod	1.733m	2.752ms	1	1	100.00
V2	chip_sw_lc_ctrl_otp_hw_cfg0	chip_sw_lc_ctrl_otp_hw_cfg0	1.788m	2.887ms	1	1	100.00
V2	chip_sw_lc_ctrl_init	chip_sw_lc_ctrl_transition	7.405m	11.569ms	1	1	100.00
V2	chip_sw_lc_ctrl_transitions	chip_sw_lc_ctrl_transition	7.405m	11.569ms	1	1	100.00
V2	chip_sw_lc_ctrl_kmac_req	chip_sw_lc_ctrl_transition	7.405m	11.569ms	1	1	100.00
V2	chip_sw_lc_ctrl_key_div	chip_sw_keymgr_key_derivation_prod	21.586m	10.493ms	1	1	100.00
V2	chip_sw_lc_ctrl_broadcast	chip_sw_flash_ctrl_lc_rw_en	4.310m	4.593ms	1	1	100.00
		chip_sw_flash_rma_unlocked	1.052h	43.752ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_test_unlocked0	3.836m	3.332ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_dev	6.835m	6.330ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_prod	9.334m	7.018ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_rma	8.952m	6.222ms	1	1	100.00
		chip_sw_lc_ctrl_transition	7.405m	11.569ms	1	1	100.00
		chip_sw_keymgr_key_derivation	13.555m	6.485ms	1	1	100.00
		chip_sw_rom_ctrl_integrity_check	4.565m	9.873ms	1	1	100.00
		chip_sw_sram_ctrl_execution_main	6.788m	8.674ms	1	1	100.00
		chip_prim_tl_access	2.533m	6.501ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_lc	5.932m	6.742ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	6.240m	4.026ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	6.351m	4.496ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	6.475m	3.800ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	6.499m	5.068ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	5.962m	4.161ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	6.630m	4.913ms	1	1	100.00
		chip_tap_straps_dev	18.738m	17.695ms	1	1	100.00
		chip_tap_straps_rma	6.021m	6.193ms	1	1	100.00
		chip_tap_straps_prod	1.733m	2.752ms	1	1	100.00
		chip_rv_dm_lc_disabled	3.125m	7.785ms	0	1	0.00
V2	chip_lc_scrap	chip_sw_lc_ctrl_rma_to_scrap	2.300m	3.044ms	1	1	100.00
		chip_sw_lc_ctrl_raw_to_scrap	1.875m	3.900ms	1	1	100.00
		chip_sw_lc_ctrl_test_locked0_to_scrap	1.859m	3.708ms	1	1	100.00
		chip_sw_lc_ctrl_rand_to_scrap	1.390m	3.061ms	1	1	100.00
V2	chip_lc_test_locked	chip_sw_lc_walkthrough_testunlocks	20.610m	28.241ms	1	1	100.00
		chip_rv_dm_lc_disabled	3.125m	7.785ms	0	1	0.00
V2	chip_sw_lc_walkthrough	chip_sw_lc_walkthrough_dev	1.051h	49.967ms	1	1	100.00
		chip_sw_lc_walkthrough_prod	1.058h	46.172ms	1	1	100.00
		chip_sw_lc_walkthrough_prodend	9.851m	10.070ms	1	1	100.00
		chip_sw_lc_walkthrough_rma	1.024h	49.064ms	1	1	100.00
		chip_sw_lc_walkthrough_testunlocks	20.610m	28.241ms	1	1	100.00
V2	chip_sw_lc_ctrl_volatile_raw_unlock	chip_sw_lc_ctrl_volatile_raw_unlock	1.400m	2.502ms	1	1	100.00
		chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz	1.214m	2.810ms	1	1	100.00
		rom_volatile_raw_unlock	1.250m	2.353ms	1	1	100.00
V2	chip_sw_otbn_op	chip_sw_otbn_ecdsa_op_irq	54.154m	17.226ms	1	1	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en	55.655m	19.085ms	1	1	100.00
V2	chip_sw_otbn_rnd_entropy	chip_sw_otbn_randomness	9.775m	5.677ms	1	1	100.00
V2	chip_sw_otbn_urnd_entropy	chip_sw_otbn_randomness	9.775m	5.677ms	1	1	100.00
V2	chip_sw_otbn_idle	chip_sw_otbn_randomness	9.775m	5.677ms	1	1	100.00
V2	chip_sw_otbn_mem_scramble	chip_sw_otbn_mem_scramble	5.306m	3.466ms	1	1	100.00
V2	chip_otp_ctrl_init	chip_sw_lc_ctrl_transition	7.405m	11.569ms	1	1	100.00
V2	chip_sw_otp_ctrl_keys	chip_sw_flash_init	21.377m	22.755ms	1	1	100.00
		chip_sw_otbn_mem_scramble	5.306m	3.466ms	1	1	100.00
		chip_sw_keymgr_key_derivation	13.555m	6.485ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access	6.950m	5.308ms	1	1	100.00
		chip_sw_rv_core_ibex_icache_invalidate	2.638m	3.088ms	1	1	100.00
V2	chip_sw_otp_ctrl_entropy	chip_sw_flash_init	21.377m	22.755ms	1	1	100.00
		chip_sw_otbn_mem_scramble	5.306m	3.466ms	1	1	100.00
		chip_sw_keymgr_key_derivation	13.555m	6.485ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access	6.950m	5.308ms	1	1	100.00
		chip_sw_rv_core_ibex_icache_invalidate	2.638m	3.088ms	1	1	100.00
V2	chip_sw_otp_ctrl_program	chip_sw_lc_ctrl_transition	7.405m	11.569ms	1	1	100.00
V2	chip_sw_otp_ctrl_program_error	chip_sw_lc_ctrl_program_error	5.301m	5.708ms	1	1	100.00
V2	chip_sw_otp_ctrl_hw_cfg0	chip_sw_lc_ctrl_otp_hw_cfg0	1.788m	2.887ms	1	1	100.00
V2	chip_sw_otp_ctrl_lc_signals	chip_sw_otp_ctrl_lc_signals_test_unlocked0	3.836m	3.332ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_dev	6.835m	6.330ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_prod	9.334m	7.018ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_rma	8.952m	6.222ms	1	1	100.00
		chip_sw_lc_ctrl_transition	7.405m	11.569ms	1	1	100.00
		chip_prim_tl_access	2.533m	6.501ms	1	1	100.00
V2	chip_sw_otp_prim_tl_access	chip_prim_tl_access	2.533m	6.501ms	1	1	100.00
V2	chip_sw_otp_ctrl_dai_lock	chip_sw_otp_ctrl_dai_lock	20.097m	10.108ms	1	1	100.00
V2	chip_sw_pwrmgr_external_full_reset	chip_sw_pwrmgr_full_aon_reset	5.284m	7.685ms	1	1	100.00
V2	chip_sw_pwrmgr_random_sleep_all_wake_ups	chip_sw_pwrmgr_random_sleep_all_wake_ups	17.704m	23.321ms	1	1	100.00
V2	chip_sw_pwrmgr_normal_sleep_all_wake_ups	chip_sw_pwrmgr_normal_sleep_all_wake_ups	3.683m	7.172ms	1	1	100.00
V2	chip_sw_pwrmgr_deep_sleep_por_reset	chip_sw_pwrmgr_deep_sleep_por_reset	7.512m	9.749ms	1	1	100.00
V2	chip_sw_pwrmgr_normal_sleep_por_reset	chip_sw_pwrmgr_normal_sleep_por_reset	6.879m	6.319ms	1	1	100.00
V2	chip_sw_pwrmgr_deep_sleep_all_wake_ups	chip_sw_pwrmgr_deep_sleep_all_wake_ups	16.795m	23.591ms	1	1	100.00
V2	chip_sw_pwrmgr_deep_sleep_all_reset_reqs	chip_sw_pwrmgr_deep_sleep_all_reset_reqs	14.474m	16.246ms	1	1	100.00
		chip_sw_aon_timer_wdog_bite_reset	7.606m	7.731ms	1	1	100.00
V2	chip_sw_pwrmgr_normal_sleep_all_reset_reqs	chip_sw_pwrmgr_normal_sleep_all_reset_reqs	12.948m	13.477ms	1	1	100.00
V2	chip_sw_pwrmgr_wdog_reset	chip_sw_pwrmgr_wdog_reset	5.644m	4.539ms	1	1	100.00
V2	chip_sw_pwrmgr_aon_power_glitch_reset	chip_sw_pwrmgr_full_aon_reset	5.284m	7.685ms	1	1	100.00
V2	chip_sw_pwrmgr_main_power_glitch_reset	chip_sw_pwrmgr_main_power_glitch_reset	2.991m	3.701ms	1	1	100.00
V2	chip_sw_pwrmgr_random_sleep_power_glitch_reset	chip_sw_pwrmgr_random_sleep_power_glitch_reset	40.747m	40.639ms	1	1	100.00
V2	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	3.934m	7.411ms	1	1	100.00
V2	chip_sw_pwrmgr_sleep_power_glitch_reset	chip_sw_pwrmgr_sleep_power_glitch_reset	4.951m	4.607ms	1	1	100.00
V2	chip_sw_pwrmgr_random_sleep_all_reset_reqs	chip_sw_pwrmgr_random_sleep_all_reset_reqs	22.517m	18.790ms	1	1	100.00
V2	chip_sw_pwrmgr_sysrst_ctrl_reset	chip_sw_pwrmgr_sysrst_ctrl_reset	10.767m	6.734ms	1	1	100.00
		chip_sw_pwrmgr_all_reset_reqs	19.515m	11.924ms	1	1	100.00
V2	chip_sw_pwrmgr_b2b_sleep_reset_req	chip_sw_pwrmgr_b2b_sleep_reset_req	28.407m	29.520ms	1	1	100.00
V2	chip_sw_pwrmgr_sleep_disabled	chip_sw_pwrmgr_sleep_disabled	2.604m	2.875ms	1	1	100.00
V2	chip_sw_pwrmgr_escalation_reset	chip_sw_all_escalation_resets	6.014m	4.893ms	1	1	100.00
V2	chip_sw_rom_access	chip_sw_rom_ctrl_integrity_check	4.565m	9.873ms	1	1	100.00
V2	chip_sw_rom_ctrl_integrity_check	chip_sw_rom_ctrl_integrity_check	4.565m	9.873ms	1	1	100.00
V2	chip_sw_rstmgr_non_sys_reset_info	chip_sw_pwrmgr_all_reset_reqs	19.515m	11.924ms	1	1	100.00
		chip_sw_pwrmgr_random_sleep_all_reset_reqs	22.517m	18.790ms	1	1	100.00
		chip_sw_pwrmgr_wdog_reset	5.644m	4.539ms	1	1	100.00
		chip_sw_pwrmgr_smoketest	4.699m	6.040ms	1	1	100.00
V2	chip_sw_rstmgr_sys_reset_info	chip_rv_dm_ndm_reset_req	5.456m	4.579ms	1	1	100.00
V2	chip_sw_rstmgr_cpu_info	chip_sw_rstmgr_cpu_info	4.052m	4.132ms	0	1	0.00
V2	chip_sw_rstmgr_sw_req_reset	chip_sw_rstmgr_sw_req	3.977m	3.822ms	1	1	100.00
V2	chip_sw_rstmgr_alert_info	chip_sw_rstmgr_alert_info	19.352m	12.019ms	1	1	100.00
V2	chip_sw_rstmgr_sw_rst	chip_sw_rstmgr_sw_rst	2.797m	2.736ms	1	1	100.00
V2	chip_sw_rstmgr_escalation_reset	chip_sw_all_escalation_resets	6.014m	4.893ms	1	1	100.00
V2	chip_sw_rstmgr_alert_handler_reset_enables	chip_sw_alert_handler_lpg_reset_toggle	18.849m	7.761ms	1	1	100.00
V2	chip_sw_nmi_irq	chip_sw_rv_core_ibex_nmi_irq	8.540m	4.973ms	1	1	100.00
V2	chip_sw_rv_core_ibex_rnd	chip_sw_rv_core_ibex_rnd	8.286m	4.323ms	1	1	100.00
V2	chip_sw_rv_core_ibex_address_translation	chip_sw_rv_core_ibex_address_translation	2.734m	2.852ms	1	1	100.00
V2	chip_sw_rv_core_ibex_icache_scrambled_access	chip_sw_rv_core_ibex_icache_invalidate	2.638m	3.088ms	1	1	100.00
V2	chip_sw_rv_core_ibex_fault_dump	chip_sw_rstmgr_cpu_info	4.052m	4.132ms	0	1	0.00
V2	chip_sw_rv_core_ibex_double_fault	chip_sw_rstmgr_cpu_info	4.052m	4.132ms	0	1	0.00
V2	chip_jtag_csr_rw	chip_jtag_csr_rw	25.808m	18.214ms	1	1	100.00
V2	chip_jtag_mem_access	chip_jtag_mem_access	14.196m	14.041ms	1	1	100.00
V2	chip_rv_dm_ndm_reset_req	chip_rv_dm_ndm_reset_req	5.456m	4.579ms	1	1	100.00
V2	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	4.513m	4.694ms	1	1	100.00
V2	chip_rv_dm_access_after_wakeup	chip_sw_rv_dm_access_after_wakeup	5.516m	5.657ms	1	1	100.00
V2	chip_sw_rv_dm_jtag_tap_sel	chip_tap_straps_rma	6.021m	6.193ms	1	1	100.00
V2	chip_rv_dm_lc_disabled	chip_rv_dm_lc_disabled	3.125m	7.785ms	0	1	0.00
V2	chip_sw_plic_all_irqs	chip_plic_all_irqs_0	9.394m	5.331ms	1	1	100.00
		chip_plic_all_irqs_10	4.252m	3.600ms	1	1	100.00
		chip_plic_all_irqs_20	6.268m	3.738ms	1	1	100.00
V2	chip_sw_plic_sw_irq	chip_sw_plic_sw_irq	1.727m	2.883ms	1	1	100.00
V2	chip_sw_timer	chip_sw_rv_timer_irq	2.395m	2.873ms	1	1	100.00
V2	chip_sw_spi_device_flash_mode	rom_e2e_smoke	42.726m	14.612ms	1	1	100.00
V2	chip_sw_spi_device_pass_through	chip_sw_spi_device_pass_through	8.630m	7.722ms	1	1	100.00
V2	chip_sw_spi_device_pass_through_collision	chip_sw_spi_device_pass_through_collision	2.968m	3.419ms	0	1	0.00
V2	chip_sw_spi_device_tpm	chip_sw_spi_device_tpm	3.299m	3.074ms	1	1	100.00
V2	chip_sw_spi_host_tx_rx	chip_sw_spi_host_tx_rx	3.199m	3.044ms	1	1	100.00
V2	chip_sw_sram_scrambled_access	chip_sw_sram_ctrl_scrambled_access	6.950m	5.308ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	4.499m	3.711ms	1	1	100.00
V2	chip_sw_sleep_sram_ret_contents	chip_sw_sleep_sram_ret_contents_no_scramble	5.646m	7.870ms	1	1	100.00
		chip_sw_sleep_sram_ret_contents_scramble	6.353m	8.710ms	1	1	100.00
V2	chip_sw_sram_execution	chip_sw_sram_ctrl_execution_main	6.788m	8.674ms	1	1	100.00
V2	chip_sw_sram_lc_escalation	chip_sw_all_escalation_resets	6.014m	4.893ms	1	1	100.00
		chip_sw_data_integrity_escalation	9.004m	5.516ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_reset	chip_sw_pwrmgr_sysrst_ctrl_reset	10.767m	6.734ms	1	1	100.00
		chip_sw_sysrst_ctrl_reset	18.799m	23.796ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_inputs	chip_sw_sysrst_ctrl_inputs	2.728m	3.002ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_outputs	chip_sw_sysrst_ctrl_outputs	4.072m	3.271ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_in_irq	chip_sw_sysrst_ctrl_in_irq	5.354m	4.656ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_sleep_wakeup	chip_sw_sysrst_ctrl_reset	18.799m	23.796ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_sleep_reset	chip_sw_sysrst_ctrl_reset	18.799m	23.796ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_ec_rst_l	chip_sw_sysrst_ctrl_ec_rst_l	3.628m	5.010ms	0	1	0.00
V2	chip_sw_sysrst_ctrl_flash_wp_l	chip_sw_sysrst_ctrl_ec_rst_l	3.628m	5.010ms	0	1	0.00
V2	chip_sw_sysrst_ctrl_ulp_z3_wakeup	chip_sw_sysrst_ctrl_ulp_z3_wakeup	5.142m	5.681ms	1	1	100.00
		chip_sw_adc_ctrl_sleep_debug_cable_wakeup	54.287m	34.876ms	0	1	0.00
V2	chip_sw_usbdev_vbus	chip_sw_usbdev_vbus	2.302m	2.908ms	1	1	100.00
V2	chip_sw_usbdev_pullup	chip_sw_usbdev_pullup	2.342m	2.974ms	1	1	100.00
V2	chip_sw_usbdev_aon_pullup	chip_sw_usbdev_aon_pullup	5.341m	3.737ms	1	1	100.00
V2	chip_sw_usbdev_setup_rx	chip_sw_usbdev_setuprx	5.192m	4.258ms	1	1	100.00
V2	chip_sw_usbdev_config_host	chip_sw_usbdev_config_host	17.432m	7.999ms	1	1	100.00
V2	chip_sw_usbdev_pincfg	chip_sw_usbdev_pincfg	1.460h	31.447ms	1	1	100.00
V2	chip_sw_usbdev_tx_rx	chip_sw_usbdev_dpi	30.914m	12.276ms	1	1	100.00
V2	chip_sw_usbdev_toggle_restore	chip_sw_usbdev_toggle_restore	2.615m	2.868ms	1	1	100.00
V2		TOTAL			236	275	85.82
V2S	chip_sw_aes_masking_off	chip_sw_aes_masking_off	3.004m	3.148ms	1	1	100.00
V2S	chip_sw_rv_core_ibex_lockstep_glitch	chip_sw_rv_core_ibex_lockstep_glitch	1.666m	2.857ms	0	1	0.00
V2S		TOTAL			1	2	50.00
V3	chip_sw_coremark	chip_sw_coremark	2.703h	72.491ms	1	1	100.00
V3	chip_sw_power_max_load	chip_sw_power_virus	6.653m	4.103ms	0	1	0.00
V3	rom_e2e_debug	rom_e2e_jtag_debug_test_unlocked0	19.380m	10.736ms	1	1	100.00
		rom_e2e_jtag_debug_dev	9.238m	14.314ms	0	1	0.00
		rom_e2e_jtag_debug_rma	19.504m	11.165ms	1	1	100.00
V3	rom_e2e_jtag_inject	rom_e2e_jtag_inject_test_unlocked0	4.309m	4.961ms	1	1	100.00
		rom_e2e_jtag_inject_dev	2.539m	4.333ms	1	1	100.00
		rom_e2e_jtag_inject_rma	3.396m	4.717ms	1	1	100.00
V3	rom_e2e_self_hash	rom_e2e_self_hash	10.425s		0	1	0.00
V3	chip_sw_clkmgr_jitter_cycle_measurements	chip_sw_clkmgr_jitter_frequency	8.085m	5.482ms	1	1	100.00
V3	chip_sw_edn_boot_mode	chip_sw_edn_boot_mode	4.650m	2.517ms	1	1	100.00
V3	chip_sw_edn_auto_mode	chip_sw_edn_auto_mode	17.062m	6.597ms	1	1	100.00
V3	chip_sw_edn_sw_mode	chip_sw_edn_sw_mode	26.791m	11.057ms	1	1	100.00
V3	chip_sw_edn_kat	chip_sw_edn_kat	3.602m	2.563ms	1	1	100.00
V3	chip_sw_flash_memory_protection	chip_sw_flash_ctrl_mem_protection	8.848m	4.773ms	1	1	100.00
V3	chip_sw_otp_ctrl_vendor_test_csr_access	chip_sw_otp_ctrl_vendor_test_csr_access	2.441m	2.834ms	1	1	100.00
V3	chip_sw_otp_ctrl_escalation	chip_sw_otp_ctrl_escalation	6.742m	5.710ms	1	1	100.00
V3	chip_sw_sensor_ctrl_deep_sleep_wake_up	chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up	5.960m	6.909ms	0	1	0.00
V3	chip_sw_pwrmgr_usb_clk_disabled_when_active	chip_sw_pwrmgr_usb_clk_disabled_when_active	4.247m	4.187ms	1	1	100.00
V3	chip_sw_all_resets	chip_sw_pwrmgr_all_reset_reqs	19.515m	11.924ms	1	1	100.00
V3	chip_rv_dm_perform_debug	rom_e2e_jtag_debug_test_unlocked0	19.380m	10.736ms	1	1	100.00
		rom_e2e_jtag_debug_dev	9.238m	14.314ms	0	1	0.00
		rom_e2e_jtag_debug_rma	19.504m	11.165ms	1	1	100.00
V3	chip_sw_rv_dm_access_after_hw_reset	chip_sw_rv_dm_access_after_escalation_reset	4.443m	3.946ms	1	1	100.00
V3	chip_sw_plic_alerts	chip_sw_all_escalation_resets	6.014m	4.893ms	1	1	100.00
V3	tick_configuration	chip_sw_rv_timer_systick_test	1.539h	37.913ms	1	1	100.00
V3	counter_wrap	chip_sw_rv_timer_systick_test	1.539h	37.913ms	1	1	100.00
V3	chip_sw_spi_device_output_when_disabled_or_sleeping	chip_sw_spi_device_pinmux_sleep_retention	3.087m	3.081ms	1	1	100.00
V3	chip_sw_uart_watermarks	chip_sw_uart_tx_rx	6.236m	3.766ms	1	1	100.00
V3	chip_sw_usbdev_stream	chip_sw_usbdev_stream	52.977m	18.869ms	1	1	100.00
V3		TOTAL			19	23	82.61
	Unmapped tests	chip_sival_flash_info_access	2.316m	2.664ms	1	1	100.00
		chip_sw_rstmgr_rst_cnsty_escalation	6.132m	5.180ms	1	1	100.00
		chip_sw_otp_ctrl_rot_auth_config	40.920m	37.248ms	0	1	0.00
		chip_sw_otp_ctrl_ecc_error_vendor_test	2.109m	2.235ms	1	1	100.00
		chip_sw_otp_ctrl_descrambling	2.695m	3.131ms	1	1	100.00
		chip_sw_pwrmgr_lowpower_cancel	3.810m	4.102ms	1	1	100.00
		chip_sw_pwrmgr_sleep_wake_5_bug	11.284s		0	1	0.00
		chip_sw_flash_ctrl_write_clear	3.244m	3.128ms	1	1	100.00
		TOTAL			279	326	85.58

Failure Buckets

UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_*.signed.*.scr.vmem could not be opened for r mode has 11 failures:
- Test rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0 has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0.112992219468967451030992515547059051419847981032829503457259392916845230079049
    Line 507, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0/latest/run.log
```
  UVM_FATAL @  10.320001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.320001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_bad_b_good_dev has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_bad_b_good_dev.44360263884286116632574882818924653531843416992320806206173166569521322118744
    Line 504, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_dev/latest/run.log
```
  UVM_FATAL @  10.160001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.160001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_bad_b_good_prod has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_bad_b_good_prod.80015038990503098107271737695338297985928380149807453760743580824318753653298
    Line 506, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod/latest/run.log
```
  UVM_FATAL @  10.340001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.340001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_bad_b_good_prod_end has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_bad_b_good_prod_end.65585087266803687663900643175460986985858339874834192834731916806052262645403
    Line 511, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod_end/latest/run.log
```
  UVM_FATAL @  10.320001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.320001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_bad_b_good_rma has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_bad_b_good_rma.34492700501528740195172952043729084422764580642492509301187701231040788635131
    Line 516, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_rma/latest/run.log
```
  UVM_FATAL @  10.280001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.280001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- ... and 6 more tests.
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_*.signed.*.scr.vmem could not be opened for r mode has 5 failures:
- Test rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0 has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0.70035373377007981252316598031520392099817111798923271481936385732217349237808
    Line 492, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0/latest/run.log
```
  UVM_FATAL @  10.100001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.100001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_good_b_bad_dev has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_good_b_bad_dev.33879263491235613588138994663913927131506502022092082321503150355099613507499
    Line 478, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_dev/latest/run.log
```
  UVM_FATAL @  10.360001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.360001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_good_b_bad_prod has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_good_b_bad_prod.95648020180282969962057285732448022077588859785542483728672061696034755481711
    Line 507, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod/latest/run.log
```
  UVM_FATAL @  10.400001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.400001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_good_b_bad_prod_end has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_good_b_bad_prod_end.21962774622485361616321224022811651556066468935322437537378411531739977349596
    Line 509, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod_end/latest/run.log
```
  UVM_FATAL @  10.280001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.280001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_good_b_bad_rma has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_good_b_bad_rma.18850730105372798719136244458068740111404937138475961946117419901541358540308
    Line 509, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_rma/latest/run.log
```
  UVM_FATAL @  10.140001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.140001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_*.signed.*.scr.vmem could not be opened for r mode has 3 failures:
- Test rom_e2e_sigverify_always_a_nothing_b_bad_prod has 1 failures.
  - 0.rom_e2e_sigverify_always_a_nothing_b_bad_prod.62345368962187068376308377792890819600402036896333363211693873644691835608349
    Line 473, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod/latest/run.log
```
  UVM_FATAL @  10.120001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.120001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_sigverify_always_a_nothing_b_bad_prod_end has 1 failures.
  - 0.rom_e2e_sigverify_always_a_nothing_b_bad_prod_end.113556036253026336810897647474295667364987288906486586648474980273403209448801
    Line 552, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod_end/latest/run.log
```
  UVM_FATAL @  10.280001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.280001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_sigverify_always_a_nothing_b_bad_rma has 1 failures.
  - 0.rom_e2e_sigverify_always_a_nothing_b_bad_rma.19396168948252424809785554081482800654572299713340959106150649026749069416056
    Line 530, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_rma/latest/run.log
```
  UVM_FATAL @  10.220001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.220001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

Job returned non-zero exit code has 2 failures:

Test chip_sw_pwrmgr_sleep_wake_5_bug has 1 failures.

0.chip_sw_pwrmgr_sleep_wake_5_bug.37169472590057789346565429172910869202777625498251341155152823737074443545006
Log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_pwrmgr_sleep_wake_5_bug/latest/run.log

  Computing main repo mapping:
  Loading:
  Loading: 0 packages loaded
  WARNING: Target pattern parsing failed.
  ERROR: Skipping '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD
  ERROR: no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD
  INFO: Elapsed time: 0.915s
  INFO: 0 processes.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

Test rom_e2e_self_hash has 1 failures.

0.rom_e2e_self_hash.16765510144034565586587295534018198886124508824246300310765288011150230231218
Log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_self_hash/latest/run.log

  Computing main repo mapping:
  Loading:
  Loading: 0 packages loaded
  WARNING: Target pattern parsing failed.
  ERROR: Skipping '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD
  ERROR: no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD
  INFO: Elapsed time: 0.155s
  INFO: 0 processes.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_test_key_*.signed.*.scr.vmem could not be opened for r mode has 2 failures:
- Test rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0 has 1 failures.
  - 0.rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0.111459794183781784974943547952500756253963342743626798859922849614639060204920
    Line 568, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0/latest/run.log
```
  UVM_FATAL @  10.240001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_test_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.240001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0 has 1 failures.
  - 0.rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0.36601930816380534527354605124032329140376733211030666180251817413512815570056
    Line 524, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0/latest/run.log
```
  UVM_FATAL @  10.200001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_test_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.200001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_dev_key_*.signed.*.scr.vmem could not be opened for r mode has 2 failures:
- Test rom_e2e_sigverify_always_a_bad_b_bad_dev has 1 failures.
  - 0.rom_e2e_sigverify_always_a_bad_b_bad_dev.60602330861090686167246218139152543096227512025579818026445040697547162892827
    Line 558, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_bad_dev/latest/run.log
```
  UVM_FATAL @  10.200001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_dev_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.200001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_sigverify_always_a_bad_b_nothing_dev has 1 failures.
  - 0.rom_e2e_sigverify_always_a_bad_b_nothing_dev.92662357597493388325737885671764023041846130374756313708571672307228531703985
    Line 501, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_nothing_dev/latest/run.log
```
  UVM_FATAL @  10.300001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_dev_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.300001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (chip_sw_sleep_pin_mio_dio_val_vseq.sv:92) [chip_sw_sleep_pin_mio_dio_val_vseq] Check failed cfg.chip_vif.mios_if.pins[i] === exp (* [*] vs *xz [z]) for MIO[*] has 1 failures:
- Test chip_sw_sleep_pin_mio_dio_val has 1 failures.
  - 0.chip_sw_sleep_pin_mio_dio_val.1537372838909232377897544391551908564924855426317008919193778776991656102295
    Line 604, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_sleep_pin_mio_dio_val/latest/run.log
```
  UVM_ERROR @ 3219.452000 us: (chip_sw_sleep_pin_mio_dio_val_vseq.sv:92) [uvm_test_top.env.virtual_sequencer.chip_sw_sleep_pin_mio_dio_val_vseq] Check failed cfg.chip_vif.mios_if.pins[i] === exp (0x0 [0] vs 0xz [z]) for MIO[30]
  UVM_INFO @ 3219.452000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:379)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty has 1 failures:
- Test chip_sw_spi_device_pass_through_collision has 1 failures.
  - 0.chip_sw_spi_device_pass_through_collision.10993218950405204003110960401817260653887934837614421953795689536597897066775
    Line 401, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_spi_device_pass_through_collision/latest/run.log
```
  UVM_ERROR @ 3418.921304 us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:379)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty
  UVM_INFO @ 3418.921304 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [otp_ctrl_rot_auth_config_test_sim_dv(sw/device/tests/otp_ctrl_rot_auth_config_test.c:22)] CHECK-STATUS-fail: @@@:* = ErrorError has 1 failures:
- Test chip_sw_otp_ctrl_rot_auth_config has 1 failures.
  - 0.chip_sw_otp_ctrl_rot_auth_config.65901732919370709898527476574960841464456798030565169106039674439558949248580
    Line 436, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_otp_ctrl_rot_auth_config/latest/run.log
```
  UVM_ERROR @ 37247.787161 us: (sw_logger_if.sv:526) [otp_ctrl_rot_auth_config_test_sim_dv(sw/device/tests/otp_ctrl_rot_auth_config_test.c:22)] CHECK-STATUS-fail: @@@:0 = ErrorError
  UVM_INFO @ 37247.787161 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@91596) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_sw_rstmgr_cpu_info has 1 failures.

0.chip_sw_rstmgr_cpu_info.96259882415076489658249689383611644666623279832608776830128448519000906642675
Line 415, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_rstmgr_cpu_info/latest/run.log

  UVM_ERROR @ 4131.707976 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (1 [0x1] vs 0 [0x0]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@91596) { a_addr: 'h8  a_data: 'h0  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h1  a_opcode: 'h0  a_user: 'h259aa  d_param: 'h0  d_source: 'h1  d_data: 'h0  d_size: 'h2  d_opcode: 'h0  d_error: 'h1  d_sink: 'h0  d_user: 'h1f2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 4131.707976 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL @ * us: (chip_sw_sysrst_ctrl_ec_rst_l_vseq.sv:138) [chip_sw_sysrst_ctrl_ec_rst_l_vseq] Timed out waiting for ec_rst to go high. has 1 failures:
- Test chip_sw_sysrst_ctrl_ec_rst_l has 1 failures.
  - 0.chip_sw_sysrst_ctrl_ec_rst_l.77061260986050805542700434502573588899232439459089631054853511555610363946486
    Line 393, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_sysrst_ctrl_ec_rst_l/latest/run.log
```
  UVM_FATAL @ 5010.380001 us: (chip_sw_sysrst_ctrl_ec_rst_l_vseq.sv:138) [uvm_test_top.env.virtual_sequencer.chip_sw_sysrst_ctrl_ec_rst_l_vseq] Timed out waiting for ec_rst to go high.
  UVM_INFO @ 5010.380001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (chip_sw_base_vseq.sv:317) virtual_sequencer [chip_sw_adc_ctrl_sleep_debug_cable_wakeup_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = * ns has 1 failures:
- Test chip_sw_adc_ctrl_sleep_debug_cable_wakeup has 1 failures.
  - 0.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.54753193293120991629622896710135778299952101272428117150613642887825905510531
    Line 414, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_adc_ctrl_sleep_debug_cable_wakeup/latest/run.log
```
  UVM_ERROR @ 34875.711046 us: (chip_sw_base_vseq.sv:317) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_adc_ctrl_sleep_debug_cable_wakeup_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = 18000000 ns

  UVM_INFO @ 34875.711046 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_test_sim_dv(hw/top_earlgrey/sw/autogen/tests/alert_test.c:307)] CHECK-fail: Expect alert *! has 1 failures:
- Test chip_sw_alert_test has 1 failures.
  - 0.chip_sw_alert_test.85868502561315792020646734232572117685996196221858816147653736079030531219561
    Line 391, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_alert_test/latest/run.log
```
  UVM_ERROR @ 2963.783940 us: (sw_logger_if.sv:526) [alert_test_sim_dv(hw/top_earlgrey/sw/autogen/tests/alert_test.c:307)] CHECK-fail: Expect alert 42!
  UVM_INFO @ 2963.783940 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0) has 1 failures:
- Test chip_sw_alert_handler_lpg_sleep_mode_alerts has 1 failures.
  - 0.chip_sw_alert_handler_lpg_sleep_mode_alerts.81733806686331740054122049214997684900819639640110454699135983359616956218154
    Line 392, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log
```
  UVM_ERROR @ 3290.086350 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
  UVM_INFO @ 3290.086350 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Job timed out after * minutes has 1 failures:
- Test chip_sw_alert_handler_lpg_sleep_mode_pings has 1 failures.
  - 0.chip_sw_alert_handler_lpg_sleep_mode_pings.104796331452836945263012851065838255753066501869161588351930405479315358728371
    Log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_alert_handler_lpg_sleep_mode_pings/latest/run.log
```
  Job timed out after 240 minutes
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [hmac_functest_sim_dv(sw/device/tests/crypto/hmac_functest.c:79)] Finished test run_test_vector: *. has 1 failures:
- Test chip_sw_hmac_oneshot has 1 failures.
  - 0.chip_sw_hmac_oneshot.94340977828670809837083475218981302233093879446470277743961578110803098960388
    Line 398, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_hmac_oneshot/latest/run.log
```
  UVM_ERROR @ 3087.303993 us: (sw_logger_if.sv:526) [hmac_functest_sim_dv(sw/device/tests/crypto/hmac_functest.c:79)] Finished test run_test_vector: 8000534a.
  UVM_INFO @ 3087.303993 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@31948) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_tl_errors has 1 failures.

0.chip_tl_errors.14795877131421326271407709992478797271004975485153320772938548649771862345611
Line 214, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_tl_errors/latest/run.log

  UVM_ERROR @ 2912.227427 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@31948) { a_addr: 'h10444  a_data: 'h565f2c69  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h1c  a_opcode: 'h4  a_user: 'h1b183  d_param: 'h0  d_source: 'h1c  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 2912.227427 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (sw_logger_if.sv:526) [pwrmgr_sensor_ctrl_deep_sleep_wake_up_sim_dv(sw/device/tests/pwrmgr_sensor_ctrl_deep_sleep_wake_up.c:120)] CHECK-STATUS-fail: @@@:* = ErrorError has 1 failures:
- Test chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up has 1 failures.
  - 0.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up.13203181722884095997077212526096400764505926780451469405215231319672065994447
    Line 405, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up/latest/run.log
```
  UVM_ERROR @ 6909.482280 us: (sw_logger_if.sv:526) [pwrmgr_sensor_ctrl_deep_sleep_wake_up_sim_dv(sw/device/tests/pwrmgr_sensor_ctrl_deep_sleep_wake_up.c:120)] CHECK-STATUS-fail: @@@:0 = ErrorError
  UVM_INFO @ 6909.482280 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (cip_base_vseq.sv:642) [chip_rv_dm_lc_disabled_vseq] Check failed masked_data == exp_data (* [*] vs * [*]) addr * read out mismatch has 1 failures:
- Test chip_rv_dm_lc_disabled has 1 failures.
  - 0.chip_rv_dm_lc_disabled.76496468366818695753921517414157744691937627836868472577261081683377246037281
    Line 228, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_rv_dm_lc_disabled/latest/run.log
```
  UVM_ERROR @ 7784.740356 us: (cip_base_vseq.sv:642) [uvm_test_top.env.virtual_sequencer.chip_rv_dm_lc_disabled_vseq] Check failed masked_data == exp_data (0 [0x0] vs 4294967295 [0xffffffff]) addr 0x10338 read out mismatch
  UVM_INFO @ 7784.740356 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (chip_sw_rv_core_ibex_lockstep_glitch_vseq.sv:714) [chip_sw_rv_core_ibex_lockstep_glitch_vseq] Check failed alert_major_internal == exp_alert_major_internal (* [*] vs * [*]) Major alert did not match expectation. has 1 failures:
- Test chip_sw_rv_core_ibex_lockstep_glitch has 1 failures.
  - 0.chip_sw_rv_core_ibex_lockstep_glitch.56050339537649266321877820803078326561900698502041724771017377503591667434982
    Line 409, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_rv_core_ibex_lockstep_glitch/latest/run.log
```
  UVM_FATAL @ 2856.973692 us: (chip_sw_rv_core_ibex_lockstep_glitch_vseq.sv:714) [uvm_test_top.env.virtual_sequencer.chip_sw_rv_core_ibex_lockstep_glitch_vseq] Check failed alert_major_internal == exp_alert_major_internal (0 [0x0] vs 1 [0x1]) Major alert did not match expectation.
  UVM_INFO @ 2856.973692 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (chip_sw_power_idle_load_vseq.sv:91) virtual_sequencer [chip_sw_power_idle_load_vseq] PWMCH* : pkt* Clock period is wrong. rcv : * exp : * has 1 failures:
- Test chip_sw_power_idle_load has 1 failures.
  - 0.chip_sw_power_idle_load.113746556325165305539001495960796783068403412792682073572179634372489978547414
    Line 395, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_power_idle_load/latest/run.log
```
  UVM_ERROR @ 3369.044000 us: (chip_sw_power_idle_load_vseq.sv:91) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_power_idle_load_vseq] PWMCH5 : pkt3 Clock period is wrong.  rcv : 2  exp : 32
  UVM_INFO @ 3369.044000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (chip_sw_power_sleep_load_vseq.sv:114) virtual_sequencer [chip_sw_power_sleep_load_vseq] PWMCH* : pkt* Clock period is wrong. rcv : * exp : * has 1 failures:
- Test chip_sw_power_sleep_load has 1 failures.
  - 0.chip_sw_power_sleep_load.1391518071197588576064965541975069496389772016332594906215137358507254744411
    Line 402, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_power_sleep_load/latest/run.log
```
  UVM_ERROR @ 3083.432500 us: (chip_sw_power_sleep_load_vseq.sv:114) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_power_sleep_load_vseq] PWMCH5 : pkt3 Clock period is wrong.  rcv : 2  exp : 32
  UVM_INFO @ 3083.432500 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [ast_clk_rst_inputs_sim_dv(sw/device/tests/sim_dv/ast_clk_rst_inputs.c:147)] CHECK-fail: Recov alert not correctly observed in alert handler has 1 failures:
- Test chip_sw_ast_clk_rst_inputs has 1 failures.
  - 0.chip_sw_ast_clk_rst_inputs.73026529351075574792490741164027447315590197873783995810286496198782688690475
    Line 415, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_ast_clk_rst_inputs/latest/run.log
```
  UVM_ERROR @ 22425.744834 us: (sw_logger_if.sv:526) [ast_clk_rst_inputs_sim_dv(sw/device/tests/sim_dv/ast_clk_rst_inputs.c:147)] CHECK-fail: Recov alert not correctly observed in alert handler
  UVM_INFO @ 22425.744834 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (chip_sw_power_virus_vseq.sv:196) [chip_sw_power_virus_vseq] Check failed csrng_acmd_q >= * (* [*] vs * [*]) has 1 failures:
- Test chip_sw_power_virus has 1 failures.
  - 0.chip_sw_power_virus.12327039740221273265798252105416592595090496255263447418626485449118135359551
    Line 453, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_power_virus/latest/run.log
```
  UVM_ERROR @ 4102.591851 us: (chip_sw_power_virus_vseq.sv:196) [uvm_test_top.env.virtual_sequencer.chip_sw_power_virus_vseq] Check failed csrng_acmd_q >= 2 (1 [0x1] vs 2 [0x2])
  UVM_INFO @ 4102.591851 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_test_key_*.signed.*.scr.vmem could not be opened for r mode has 1 failures:
- Test rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0 has 1 failures.
  - 0.rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0.49168377818268418281905259884050400987020038785050631841238211701581655112084
    Line 486, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0/latest/run.log
```
  UVM_FATAL @  10.140001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_test_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.140001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_dev_key_*.signed.*.scr.vmem could not be opened for r mode has 1 failures:
- Test rom_e2e_sigverify_always_a_nothing_b_bad_dev has 1 failures.
  - 0.rom_e2e_sigverify_always_a_nothing_b_bad_dev.95031998191450587254508022599301670729325396124073233701446351481398080007072
    Line 500, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_dev/latest/run.log
```
  UVM_FATAL @  10.380001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_dev_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.380001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (jtag_rv_debugger.sv:113) [debugger] timeout occurred! has 1 failures:
- Test rom_e2e_jtag_debug_dev has 1 failures.
  - 0.rom_e2e_jtag_debug_dev.82077782017924463055318805343416444101049279982689779659393329033771676317803
    Line 440, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_jtag_debug_dev/latest/run.log
```
  UVM_FATAL @ 14314.288125 us: (jtag_rv_debugger.sv:113) [debugger] timeout occurred!
  UVM_INFO @ 14314.288125 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@31960) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_csr_mem_rw_with_rand_reset has 1 failures.

0.chip_csr_mem_rw_with_rand_reset.36793914894899805064891075989880390981275355891023068968838306510423074906422
Line 221, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_csr_mem_rw_with_rand_reset/latest/run.log

  UVM_ERROR @ 1954.098978 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@31960) { a_addr: 'h10604  a_data: 'h59024ce1  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'hd  a_opcode: 'h4  a_user: 'h19275  d_param: 'h0  d_source: 'hd  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 1954.098978 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---